| Message ID | 20231225084424.30986-6-quic_luoj@quicinc.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | support ipq5332 platform | expand |
On 25/12/2023 09:44, Luo Jie wrote: > Update the yaml file for the new DTS properties. > > 1. qcom,cmn-ref-clock-frequency for the CMN PLL source clock select. > 2. clock-frequency for MDIO clock frequency config. > 3. add uniphy AHB & SYS GCC clocks. I see two new compatibles, so your list is missing main point. > > Signed-off-by: Luo Jie <quic_luoj@quicinc.com> > --- > .../bindings/net/qcom,ipq4019-mdio.yaml | 141 +++++++++++++++++- > 1 file changed, 136 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml > index 3407e909e8a7..205500cb1fd1 100644 > --- a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml > +++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml > @@ -18,8 +18,10 @@ properties: > > - items: > - enum: > + - qcom,ipq5332-mdio > - qcom,ipq6018-mdio > - qcom,ipq8074-mdio > + - qcom,ipq9574-mdio > - const: qcom,ipq4019-mdio > > "#address-cells": > @@ -30,19 +32,76 @@ properties: > > reg: > minItems: 1 > - maxItems: 2 > - description: > - the first Address and length of the register set for the MDIO controller. > - the second Address and length of the register for ethernet LDO, this second > - address range is only required by the platform IPQ50xx. > + maxItems: 5 > + description: | > + The first address and length of the register set for the MDIO controller, > + the optional second address and length of the register is for CMN block, > + the optional third, fourth and fifth address and length of the register > + for Ethernet LDO, the optional Ethernet LDO address range is required by Wait, required? You said in in response to Rob these are not required! > + the platform IPQ50xx/IPQ5332. So these are valid for all platforms or not? Looks not, but nothing narrows the list for other boards. Anyway, why do you add entries in the middle? LDO was the second, so it cannot be now fifth. > + > + reg-names: > + minItems: 1 > + items: > + - const: mdio > + - const: cmn_blk > + - const: eth_ldo1 > + - const: eth_ldo2 > + - const: eth_ldo3 > > clocks: > + minItems: 1 > items: > - description: MDIO clock source frequency fixed to 100MHZ > + - description: UNIPHY0 AHB clock source frequency fixed to 100MHZ > + - description: UNIPHY1 AHB clock source frequency fixed to 100MHZ > + - description: UNIPHY0 SYS clock source frequency fixed to 24MHZ > + - description: UNIPHY1 SYS clock source frequency fixed to 24MHZ > > clock-names: > + minItems: 1 > items: > - const: gcc_mdio_ahb_clk > + - const: uniphy0_ahb > + - const: uniphy1_ahb > + - const: uniphy0_sys > + - const: uniphy1_sys > + > + qcom,cmn-ref-clock-frequency: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: > + - 25000000 > + - 31250000 > + - 40000000 > + - 48000000 > + - 50000000 > + - 96000000 > + default: 48000000 > + description: | > + The reference clock source of CMN PLL block is selectable, the > + reference clock source can be from wifi module or the external > + xtal, the reference clock frequency 48MHZ can be from internal > + wifi or the external xtal, if absent, the internal 48MHZ is used, > + if the 48MHZ is specified, which means the external 48Mhz is used. This does not resolve mine and Conor's concerns from previous version. External clocks are defined as clock inputs. > + > + clock-frequency: > + enum: > + - 390625 > + - 781250 > + - 1562500 > + - 3125000 > + - 6250000 > + - 12500000 > + default: 390625 > + description: | > + The MDIO bus clock that must be output by the MDIO bus hardware, > + only the listed frequencies above can be supported, other frequency > + will cause malfunction. If absent, the default hardware value 0xff > + is used, which means the default MDIO clock frequency 390625HZ, The > + MDIO clock frequency is MDIO_SYS_CLK/(MDIO_CLK_DIV + 1), the SoC > + MDIO_SYS_CLK is fixed to 100MHZ, the MDIO_CLK_DIV is from MDIO control > + register, there is higher clock frequency requirement on the normal > + working case where the MDIO slave devices support high clock frequency. > > required: > - compatible > @@ -59,8 +118,10 @@ allOf: > contains: > enum: > - qcom,ipq5018-mdio > + - qcom,ipq5332-mdio > - qcom,ipq6018-mdio > - qcom,ipq8074-mdio > + - qcom,ipq9574-mdio > then: > required: > - clocks > @@ -70,6 +131,20 @@ allOf: > clocks: false > clock-names: false > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,ipq5332-mdio > + then: > + properties: > + clocks: > + minItems: 5 > + maxItems: 5 > + reg-names: > + minItems: 4 Why all other variants now have 5 clocks and 5 reg entries? Nothing of it is explained in the commit msg. > + > unevaluatedProperties: false > > examples: > @@ -100,3 +175,59 @@ examples: > reg = <4>; > }; > }; > + > + - | > + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> > + #include <dt-bindings/gpio/gpio.h> > + > + mdio@90000 { > + #address-cells = <1>; > + #size-cells = <0>; That's not the order of properties. compatible is always the first, reg and reg-names follow. See DTS coding style. > + compatible = "qcom,ipq5332-mdio", > + "qcom,ipq4019-mdio"; > + > + reg = <0x90000 0x64>, > + <0x9b000 0x800>, > + <0x7a00610 0x4>, > + <0x7a10610 0x4>; > + Drop blank line. > + reg-names = "mdio", > + "cmn_blk", > + "eth_ldo1", > + "eth_ldo2"; > + > + clocks = <&gcc GCC_MDIO_AHB_CLK>, > + <&gcc GCC_UNIPHY0_AHB_CLK>, > + <&gcc GCC_UNIPHY1_AHB_CLK>, > + <&gcc GCC_UNIPHY0_SYS_CLK>, > + <&gcc GCC_UNIPHY1_SYS_CLK>; > + Drop blank line > + clock-names = "gcc_mdio_ahb_clk", > + "uniphy0_ahb", > + "uniphy1_ahb", > + "uniphy0_sys", > + "uniphy1_sys"; > + > + clock-frequency = <6250000>; > + reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>; > + Best regards, Krzysztof
On 12/25/2023 6:29 PM, Krzysztof Kozlowski wrote: > On 25/12/2023 09:44, Luo Jie wrote: >> Update the yaml file for the new DTS properties. >> >> 1. qcom,cmn-ref-clock-frequency for the CMN PLL source clock select. >> 2. clock-frequency for MDIO clock frequency config. >> 3. add uniphy AHB & SYS GCC clocks. > > I see two new compatibles, so your list is missing main point. will add the compatibles into the list, thanks. > >> >> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> >> --- >> .../bindings/net/qcom,ipq4019-mdio.yaml | 141 +++++++++++++++++- >> 1 file changed, 136 insertions(+), 5 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml >> index 3407e909e8a7..205500cb1fd1 100644 >> --- a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml >> +++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml >> @@ -18,8 +18,10 @@ properties: >> >> - items: >> - enum: >> + - qcom,ipq5332-mdio >> - qcom,ipq6018-mdio >> - qcom,ipq8074-mdio >> + - qcom,ipq9574-mdio >> - const: qcom,ipq4019-mdio >> >> "#address-cells": >> @@ -30,19 +32,76 @@ properties: >> >> reg: >> minItems: 1 >> - maxItems: 2 >> - description: >> - the first Address and length of the register set for the MDIO controller. >> - the second Address and length of the register for ethernet LDO, this second >> - address range is only required by the platform IPQ50xx. >> + maxItems: 5 >> + description: | >> + The first address and length of the register set for the MDIO controller, >> + the optional second address and length of the register is for CMN block, >> + the optional third, fourth and fifth address and length of the register >> + for Ethernet LDO, the optional Ethernet LDO address range is required by > > Wait, required? You said in in response to Rob these are not required! As for the response to Rob, i was saying the uniphy ahb and sys clocks are not needed on ipq9574. The LDO are needed on ipq5332 and ipq5018 currently. > >> + the platform IPQ50xx/IPQ5332. > > So these are valid for all platforms or not? Looks not, but nothing > narrows the list for other boards. i add the limitation on the reg usage for the ipq5332 platform on the following part "if condition" of this patch, i will update the patch to narrow down for the other compatibles. > > Anyway, why do you add entries in the middle? LDO was the second, so it > cannot be now fifth. As Rob's suggestion, i move the cmn_blk to second location for simplifying the limitation description, i checked the upstream dts code, the LDO is not used currently, so we can move cmn_blk to the second location here. > >> + >> + reg-names: >> + minItems: 1 >> + items: >> + - const: mdio >> + - const: cmn_blk >> + - const: eth_ldo1 >> + - const: eth_ldo2 >> + - const: eth_ldo3 >> >> clocks: >> + minItems: 1 >> items: >> - description: MDIO clock source frequency fixed to 100MHZ >> + - description: UNIPHY0 AHB clock source frequency fixed to 100MHZ >> + - description: UNIPHY1 AHB clock source frequency fixed to 100MHZ >> + - description: UNIPHY0 SYS clock source frequency fixed to 24MHZ >> + - description: UNIPHY1 SYS clock source frequency fixed to 24MHZ >> >> clock-names: >> + minItems: 1 >> items: >> - const: gcc_mdio_ahb_clk >> + - const: uniphy0_ahb >> + - const: uniphy1_ahb >> + - const: uniphy0_sys >> + - const: uniphy1_sys >> + >> + qcom,cmn-ref-clock-frequency: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: >> + - 25000000 >> + - 31250000 >> + - 40000000 >> + - 48000000 >> + - 50000000 >> + - 96000000 >> + default: 48000000 >> + description: | >> + The reference clock source of CMN PLL block is selectable, the >> + reference clock source can be from wifi module or the external >> + xtal, the reference clock frequency 48MHZ can be from internal >> + wifi or the external xtal, if absent, the internal 48MHZ is used, >> + if the 48MHZ is specified, which means the external 48Mhz is used. > > This does not resolve mine and Conor's concerns from previous version. > External clocks are defined as clock inputs. No matter the external or internal reference clock, they are the clock source selection for CMN, there are only 48MHZ can be external or internal, other clocks have the different clock rate, so the internal 48MHZ reference clock can be implied when the "qcom,cmn-ref-clock-frequency" is not defined, which is suggested by Conor in the previous comments. > >> + >> + clock-frequency: >> + enum: >> + - 390625 >> + - 781250 >> + - 1562500 >> + - 3125000 >> + - 6250000 >> + - 12500000 >> + default: 390625 >> + description: | >> + The MDIO bus clock that must be output by the MDIO bus hardware, >> + only the listed frequencies above can be supported, other frequency >> + will cause malfunction. If absent, the default hardware value 0xff >> + is used, which means the default MDIO clock frequency 390625HZ, The >> + MDIO clock frequency is MDIO_SYS_CLK/(MDIO_CLK_DIV + 1), the SoC >> + MDIO_SYS_CLK is fixed to 100MHZ, the MDIO_CLK_DIV is from MDIO control >> + register, there is higher clock frequency requirement on the normal >> + working case where the MDIO slave devices support high clock frequency. >> >> required: >> - compatible >> @@ -59,8 +118,10 @@ allOf: >> contains: >> enum: >> - qcom,ipq5018-mdio >> + - qcom,ipq5332-mdio >> - qcom,ipq6018-mdio >> - qcom,ipq8074-mdio >> + - qcom,ipq9574-mdio >> then: >> required: >> - clocks >> @@ -70,6 +131,20 @@ allOf: >> clocks: false >> clock-names: false >> >> + - if: >> + properties: >> + compatible: >> + contains: >> + enum: >> + - qcom,ipq5332-mdio >> + then: >> + properties: >> + clocks: >> + minItems: 5 >> + maxItems: 5 >> + reg-names: >> + minItems: 4 > > Why all other variants now have 5 clocks and 5 reg entries? Nothing of > it is explained in the commit msg. From the condition above, only "qcom,ipq5332-mdio" has 5 clocks (mdio + 4 uniphy clocks) and 4 regs (mdio + cmn_blk + 2 LDOs) as the cmn_blk is moved to the second location. how it can gives the 5 clocks and 5 regs for other variants here? > >> + >> unevaluatedProperties: false >> >> examples: >> @@ -100,3 +175,59 @@ examples: >> reg = <4>; >> }; >> }; >> + >> + - | >> + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> >> + #include <dt-bindings/gpio/gpio.h> >> + >> + mdio@90000 { >> + #address-cells = <1>; >> + #size-cells = <0>; > > That's not the order of properties. compatible is always the first, reg > and reg-names follow. See DTS coding style. will correct this, thanks. > >> + compatible = "qcom,ipq5332-mdio", >> + "qcom,ipq4019-mdio"; >> + >> + reg = <0x90000 0x64>, >> + <0x9b000 0x800>, >> + <0x7a00610 0x4>, >> + <0x7a10610 0x4>; >> + > > Drop blank line. Ok. > >> + reg-names = "mdio", >> + "cmn_blk", >> + "eth_ldo1", >> + "eth_ldo2"; >> + >> + clocks = <&gcc GCC_MDIO_AHB_CLK>, >> + <&gcc GCC_UNIPHY0_AHB_CLK>, >> + <&gcc GCC_UNIPHY1_AHB_CLK>, >> + <&gcc GCC_UNIPHY0_SYS_CLK>, >> + <&gcc GCC_UNIPHY1_SYS_CLK>; >> + > > Drop blank line Ok. > >> + clock-names = "gcc_mdio_ahb_clk", >> + "uniphy0_ahb", >> + "uniphy1_ahb", >> + "uniphy0_sys", >> + "uniphy1_sys"; >> + >> + clock-frequency = <6250000>; >> + reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>; >> + > > Best regards, > Krzysztof >
On 26/12/2023 08:25, Jie Luo wrote: >>> - description: >>> - the first Address and length of the register set for the MDIO controller. >>> - the second Address and length of the register for ethernet LDO, this second >>> - address range is only required by the platform IPQ50xx. >>> + maxItems: 5 >>> + description: | >>> + The first address and length of the register set for the MDIO controller, >>> + the optional second address and length of the register is for CMN block, >>> + the optional third, fourth and fifth address and length of the register >>> + for Ethernet LDO, the optional Ethernet LDO address range is required by >> >> Wait, required? You said in in response to Rob these are not required! > > As for the response to Rob, i was saying the uniphy ahb and sys clocks > are not needed on ipq9574. > The LDO are needed on ipq5332 and ipq5018 currently. Clocks as well but: "A driver can function without knowing about all these new registers and ..." Anyway, this should be list ("items:") with descriptions, instead of one big description listing things. > >> >>> + the platform IPQ50xx/IPQ5332. >> >> So these are valid for all platforms or not? Looks not, but nothing >> narrows the list for other boards. > > i add the limitation on the reg usage for the ipq5332 platform on the > following part "if condition" of this patch, i will update the patch > to narrow down for the other compatibles. > >> >> Anyway, why do you add entries in the middle? LDO was the second, so it >> cannot be now fifth. > > As Rob's suggestion, i move the cmn_blk to second location for > simplifying the limitation description, i checked the upstream dts code, > the LDO is not used currently, so we can move cmn_blk to the second > location here. I cannot find his suggestion in the previous thread. Where did he propose it? ... >>> + qcom,cmn-ref-clock-frequency: >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + enum: >>> + - 25000000 >>> + - 31250000 >>> + - 40000000 >>> + - 48000000 >>> + - 50000000 >>> + - 96000000 >>> + default: 48000000 >>> + description: | >>> + The reference clock source of CMN PLL block is selectable, the >>> + reference clock source can be from wifi module or the external >>> + xtal, the reference clock frequency 48MHZ can be from internal >>> + wifi or the external xtal, if absent, the internal 48MHZ is used, >>> + if the 48MHZ is specified, which means the external 48Mhz is used. >> >> This does not resolve mine and Conor's concerns from previous version. >> External clocks are defined as clock inputs. > > No matter the external or internal reference clock, they are the clock > source selection for CMN, there are only 48MHZ can be external or > internal, other clocks have the different clock rate, so the internal > 48MHZ reference clock can be implied when the > "qcom,cmn-ref-clock-frequency" is not defined, which is suggested by > Conor in the previous > comments. I don't think he proposed it, but maybe I missed some message (care to point me to his message where he agreed on usage of qcom,cmn-ref-clock-frequency?). I am pretty sure we both stayed on the same page, that the presence of clocks defines choice of internal clock. This property should go away. It is tiring to keep discussing this. > >> >>> + >>> + clock-frequency: >>> + enum: >>> + - 390625 >>> + - 781250 >>> + - 1562500 >>> + - 3125000 >>> + - 6250000 >>> + - 12500000 >>> + default: 390625 >>> + description: | >>> + The MDIO bus clock that must be output by the MDIO bus hardware, >>> + only the listed frequencies above can be supported, other frequency >>> + will cause malfunction. If absent, the default hardware value 0xff >>> + is used, which means the default MDIO clock frequency 390625HZ, The >>> + MDIO clock frequency is MDIO_SYS_CLK/(MDIO_CLK_DIV + 1), the SoC >>> + MDIO_SYS_CLK is fixed to 100MHZ, the MDIO_CLK_DIV is from MDIO control >>> + register, there is higher clock frequency requirement on the normal >>> + working case where the MDIO slave devices support high clock frequency. >>> >>> required: >>> - compatible >>> @@ -59,8 +118,10 @@ allOf: >>> contains: >>> enum: >>> - qcom,ipq5018-mdio >>> + - qcom,ipq5332-mdio >>> - qcom,ipq6018-mdio >>> - qcom,ipq8074-mdio >>> + - qcom,ipq9574-mdio >>> then: >>> required: >>> - clocks >>> @@ -70,6 +131,20 @@ allOf: >>> clocks: false >>> clock-names: false >>> >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + enum: >>> + - qcom,ipq5332-mdio >>> + then: >>> + properties: >>> + clocks: >>> + minItems: 5 >>> + maxItems: 5 >>> + reg-names: >>> + minItems: 4 >> >> Why all other variants now have 5 clocks and 5 reg entries? Nothing of >> it is explained in the commit msg. > > From the condition above, only "qcom,ipq5332-mdio" has 5 clocks (mdio + > 4 uniphy clocks) and 4 regs (mdio + cmn_blk + 2 LDOs) as the cmn_blk is > moved to the second location. > > how it can gives the 5 clocks and 5 regs for other variants here? How? Just read the beginning of your patch. It clearly says everyone has up to 5 reg entries and up to 5 clocks. Best regards, Krzysztof
On Tue, Dec 26, 2023 at 10:28:09AM +0100, Krzysztof Kozlowski wrote: > On 26/12/2023 08:25, Jie Luo wrote: > >>> + qcom,cmn-ref-clock-frequency: > >>> + $ref: /schemas/types.yaml#/definitions/uint32 > >>> + enum: > >>> + - 25000000 > >>> + - 31250000 > >>> + - 40000000 > >>> + - 48000000 > >>> + - 50000000 > >>> + - 96000000 > >>> + default: 48000000 > >>> + description: | > >>> + The reference clock source of CMN PLL block is selectable, the > >>> + reference clock source can be from wifi module or the external > >>> + xtal, the reference clock frequency 48MHZ can be from internal > >>> + wifi or the external xtal, if absent, the internal 48MHZ is used, > >>> + if the 48MHZ is specified, which means the external 48Mhz is used. > >> > >> This does not resolve mine and Conor's concerns from previous version. > >> External clocks are defined as clock inputs. > > > > No matter the external or internal reference clock, they are the clock > > source selection for CMN, there are only 48MHZ can be external or > > internal, other clocks have the different clock rate, so the internal > > 48MHZ reference clock can be implied when the > > "qcom,cmn-ref-clock-frequency" is not defined, which is suggested by > > Conor in the previous > > comments. > > I don't think he proposed it, but maybe I missed some message (care to > point me to his message where he agreed on usage of > qcom,cmn-ref-clock-frequency?). I am pretty sure we both stayed on the > same page, that the presence of clocks defines choice of internal clock. > This property should go away. Exactly, I wanted this property to be removed. My suggestion was about defaulting to the internal clock when the "clocks" property did not contain the cmn ref clock. > It is tiring to keep discussing this. Yup.
On 12/26/2023 5:28 PM, Krzysztof Kozlowski wrote: > On 26/12/2023 08:25, Jie Luo wrote: >>>> - description: >>>> - the first Address and length of the register set for the MDIO controller. >>>> - the second Address and length of the register for ethernet LDO, this second >>>> - address range is only required by the platform IPQ50xx. >>>> + maxItems: 5 >>>> + description: | >>>> + The first address and length of the register set for the MDIO controller, >>>> + the optional second address and length of the register is for CMN block, >>>> + the optional third, fourth and fifth address and length of the register >>>> + for Ethernet LDO, the optional Ethernet LDO address range is required by >>> >>> Wait, required? You said in in response to Rob these are not required! >> >> As for the response to Rob, i was saying the uniphy ahb and sys clocks >> are not needed on ipq9574. >> The LDO are needed on ipq5332 and ipq5018 currently. > > Clocks as well but: > > "A driver can function without knowing about all these new registers and > ..." This comments are for compatible string in V2, the MDIO drive configures the hardware according to the DTS property defined or not for the new added IPQ platforms(ipq5332 and ipq9574) support. > > Anyway, this should be list ("items:") with descriptions, instead of one > big description listing things. Ok, will update to use the list descriptions, thanks. > > >> >>> >>>> + the platform IPQ50xx/IPQ5332. >>> >>> So these are valid for all platforms or not? Looks not, but nothing >>> narrows the list for other boards. >> >> i add the limitation on the reg usage for the ipq5332 platform on the >> following part "if condition" of this patch, i will update the patch >> to narrow down for the other compatibles. >> >>> >>> Anyway, why do you add entries in the middle? LDO was the second, so it >>> cannot be now fifth. >> >> As Rob's suggestion, i move the cmn_blk to second location for >> simplifying the limitation description, i checked the upstream dts code, >> the LDO is not used currently, so we can move cmn_blk to the second >> location here. > > I cannot find his suggestion in the previous thread. Where did he > propose it? Rob suggested this on the V2 as below. " Perhaps cmn_blk should come 2nd, so all the variants have the same entry indices. Then you can move this to the top level and just say 'minItems: 4' here. " > > ... > >>>> + qcom,cmn-ref-clock-frequency: >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + enum: >>>> + - 25000000 >>>> + - 31250000 >>>> + - 40000000 >>>> + - 48000000 >>>> + - 50000000 >>>> + - 96000000 >>>> + default: 48000000 >>>> + description: | >>>> + The reference clock source of CMN PLL block is selectable, the >>>> + reference clock source can be from wifi module or the external >>>> + xtal, the reference clock frequency 48MHZ can be from internal >>>> + wifi or the external xtal, if absent, the internal 48MHZ is used, >>>> + if the 48MHZ is specified, which means the external 48Mhz is used. >>> >>> This does not resolve mine and Conor's concerns from previous version. >>> External clocks are defined as clock inputs. >> >> No matter the external or internal reference clock, they are the clock >> source selection for CMN, there are only 48MHZ can be external or >> internal, other clocks have the different clock rate, so the internal >> 48MHZ reference clock can be implied when the >> "qcom,cmn-ref-clock-frequency" is not defined, which is suggested by >> Conor in the previous >> comments. > > I don't think he proposed it, but maybe I missed some message (care to > point me to his message where he agreed on usage of > qcom,cmn-ref-clock-frequency?). I am pretty sure we both stayed on the > same page, that the presence of clocks defines choice of internal clock. > This property should go away. Sorry for this confusion. Rob said the internal reference source can be decided by the absence of the property combined with compatible string, because i said the internal 96MHZ is used on ipq5018 currently in the previous message. per double checked the current IPQ platforms, the internal 96MHZ is also possible on ipq9574, and the reference clock source should be kept as configurable instead of limited by the compatible string, maybe the different reference clock source is acquired in the future, even currently it is not used on the special platform for now. so i update the solution with a little bit of changes. > > It is tiring to keep discussing this. > >> >>> >>>> + >>>> + clock-frequency: >>>> + enum: >>>> + - 390625 >>>> + - 781250 >>>> + - 1562500 >>>> + - 3125000 >>>> + - 6250000 >>>> + - 12500000 >>>> + default: 390625 >>>> + description: | >>>> + The MDIO bus clock that must be output by the MDIO bus hardware, >>>> + only the listed frequencies above can be supported, other frequency >>>> + will cause malfunction. If absent, the default hardware value 0xff >>>> + is used, which means the default MDIO clock frequency 390625HZ, The >>>> + MDIO clock frequency is MDIO_SYS_CLK/(MDIO_CLK_DIV + 1), the SoC >>>> + MDIO_SYS_CLK is fixed to 100MHZ, the MDIO_CLK_DIV is from MDIO control >>>> + register, there is higher clock frequency requirement on the normal >>>> + working case where the MDIO slave devices support high clock frequency. >>>> >>>> required: >>>> - compatible >>>> @@ -59,8 +118,10 @@ allOf: >>>> contains: >>>> enum: >>>> - qcom,ipq5018-mdio >>>> + - qcom,ipq5332-mdio >>>> - qcom,ipq6018-mdio >>>> - qcom,ipq8074-mdio >>>> + - qcom,ipq9574-mdio >>>> then: >>>> required: >>>> - clocks >>>> @@ -70,6 +131,20 @@ allOf: >>>> clocks: false >>>> clock-names: false >>>> >>>> + - if: >>>> + properties: >>>> + compatible: >>>> + contains: >>>> + enum: >>>> + - qcom,ipq5332-mdio >>>> + then: >>>> + properties: >>>> + clocks: >>>> + minItems: 5 >>>> + maxItems: 5 >>>> + reg-names: >>>> + minItems: 4 >>> >>> Why all other variants now have 5 clocks and 5 reg entries? Nothing of >>> it is explained in the commit msg. >> >> From the condition above, only "qcom,ipq5332-mdio" has 5 clocks (mdio + >> 4 uniphy clocks) and 4 regs (mdio + cmn_blk + 2 LDOs) as the cmn_blk is >> moved to the second location. >> >> how it can gives the 5 clocks and 5 regs for other variants here? > > How? Just read the beginning of your patch. It clearly says everyone has > up to 5 reg entries and up to 5 clocks. Sorry for missing the limitation of the new added regs and clocks for other platforms, will update the patch to add the limitation usage of the reg and clocks on the other platform. Thanks! > > > > Best regards, > Krzysztof >
On 12/26/2023 8:21 PM, Conor Dooley wrote: > On Tue, Dec 26, 2023 at 10:28:09AM +0100, Krzysztof Kozlowski wrote: >> On 26/12/2023 08:25, Jie Luo wrote: > >>>>> + qcom,cmn-ref-clock-frequency: >>>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>>> + enum: >>>>> + - 25000000 >>>>> + - 31250000 >>>>> + - 40000000 >>>>> + - 48000000 >>>>> + - 50000000 >>>>> + - 96000000 >>>>> + default: 48000000 >>>>> + description: | >>>>> + The reference clock source of CMN PLL block is selectable, the >>>>> + reference clock source can be from wifi module or the external >>>>> + xtal, the reference clock frequency 48MHZ can be from internal >>>>> + wifi or the external xtal, if absent, the internal 48MHZ is used, >>>>> + if the 48MHZ is specified, which means the external 48Mhz is used. >>>> >>>> This does not resolve mine and Conor's concerns from previous version. >>>> External clocks are defined as clock inputs. >>> >>> No matter the external or internal reference clock, they are the clock >>> source selection for CMN, there are only 48MHZ can be external or >>> internal, other clocks have the different clock rate, so the internal >>> 48MHZ reference clock can be implied when the >>> "qcom,cmn-ref-clock-frequency" is not defined, which is suggested by >>> Conor in the previous >>> comments. >> >> I don't think he proposed it, but maybe I missed some message (care to >> point me to his message where he agreed on usage of >> qcom,cmn-ref-clock-frequency?). I am pretty sure we both stayed on the >> same page, that the presence of clocks defines choice of internal clock. >> This property should go away. > > Exactly, I wanted this property to be removed. My suggestion was about > defaulting to the internal clock when the "clocks" property did not > contain the cmn ref clock. There are two internal reference clock sources 48MHZ and 96MHZ. The 96MHZ is used on ipq5018 currently as i said in the previous message, but it is also possible to used on ipq9574 per double checked, since the possible reference clock source should be kept as configurable and the clock source should not be limited on the specific IPQ platform, since the clock source is configurable, the different clock source maybe required by the different board design. As description above, the reference clock source has the different clock rate except the 48MHZ, so it can imply that the internal 48MHZ used when the property is absent. > >> It is tiring to keep discussing this. > > Yup. >
On 26/12/2023 14:06, Jie Luo wrote: > >> >> >>> >>>> >>>>> + the platform IPQ50xx/IPQ5332. >>>> >>>> So these are valid for all platforms or not? Looks not, but nothing >>>> narrows the list for other boards. >>> >>> i add the limitation on the reg usage for the ipq5332 platform on the >>> following part "if condition" of this patch, i will update the patch >>> to narrow down for the other compatibles. >>> >>>> >>>> Anyway, why do you add entries in the middle? LDO was the second, so it >>>> cannot be now fifth. >>> >>> As Rob's suggestion, i move the cmn_blk to second location for >>> simplifying the limitation description, i checked the upstream dts code, >>> the LDO is not used currently, so we can move cmn_blk to the second >>> location here. >> >> I cannot find his suggestion in the previous thread. Where did he >> propose it? > > Rob suggested this on the V2 as below. > " > Perhaps cmn_blk should come 2nd, so all the variants have the same entry > indices. Then you can move this to the top level and just say 'minItems: > 4' here. Wasn't this for new devices? What about all existing which have LDO as the second entry? >>>>> + qcom,cmn-ref-clock-frequency: >>>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>>> + enum: >>>>> + - 25000000 >>>>> + - 31250000 >>>>> + - 40000000 >>>>> + - 48000000 >>>>> + - 50000000 >>>>> + - 96000000 >>>>> + default: 48000000 >>>>> + description: | >>>>> + The reference clock source of CMN PLL block is selectable, the >>>>> + reference clock source can be from wifi module or the external >>>>> + xtal, the reference clock frequency 48MHZ can be from internal >>>>> + wifi or the external xtal, if absent, the internal 48MHZ is used, >>>>> + if the 48MHZ is specified, which means the external 48Mhz is used. >>>> >>>> This does not resolve mine and Conor's concerns from previous version. >>>> External clocks are defined as clock inputs. >>> >>> No matter the external or internal reference clock, they are the clock >>> source selection for CMN, there are only 48MHZ can be external or >>> internal, other clocks have the different clock rate, so the internal >>> 48MHZ reference clock can be implied when the >>> "qcom,cmn-ref-clock-frequency" is not defined, which is suggested by >>> Conor in the previous >>> comments. >> >> I don't think he proposed it, but maybe I missed some message (care to >> point me to his message where he agreed on usage of >> qcom,cmn-ref-clock-frequency?). I am pretty sure we both stayed on the >> same page, that the presence of clocks defines choice of internal clock. >> This property should go away. > > Sorry for this confusion. > Rob said the internal reference source can be decided by the absence of > the property combined with compatible string, because i said the So all your three DT maintainers agree that lack of property for choosing clock, defines the usage of interrupt source. Now we had huge amount of arguments that you do not represent properly the clock relationships. Still. > internal 96MHZ is used on ipq5018 currently in the previous message. > > per double checked the current IPQ platforms, the internal 96MHZ is also > possible on ipq9574, and the reference clock source should be kept as > configurable instead of limited by the compatible string, maybe the > different reference clock source is acquired in the future, even > currently it is not used on the special platform for now. > > so i update the solution with a little bit of changes. You still do not want to implement our suggestions and I don't understand your arguments. Nothing in above paragraph explains me why you cannot use clock provider/consumer relationships. Best regards, Krzysztof
On 26/12/2023 14:14, Jie Luo wrote: > >>>>> >>>>> This does not resolve mine and Conor's concerns from previous version. >>>>> External clocks are defined as clock inputs. >>>> >>>> No matter the external or internal reference clock, they are the clock >>>> source selection for CMN, there are only 48MHZ can be external or >>>> internal, other clocks have the different clock rate, so the internal >>>> 48MHZ reference clock can be implied when the >>>> "qcom,cmn-ref-clock-frequency" is not defined, which is suggested by >>>> Conor in the previous >>>> comments. >>> >>> I don't think he proposed it, but maybe I missed some message (care to >>> point me to his message where he agreed on usage of >>> qcom,cmn-ref-clock-frequency?). I am pretty sure we both stayed on the >>> same page, that the presence of clocks defines choice of internal clock. >>> This property should go away. >> >> Exactly, I wanted this property to be removed. My suggestion was about >> defaulting to the internal clock when the "clocks" property did not >> contain the cmn ref clock. > > There are two internal reference clock sources 48MHZ and 96MHZ. On which devices? Paste entire picture, not half-baked descriptions. > The 96MHZ is used on ipq5018 currently as i said in the previous > message, but it is also possible to used on ipq9574 per double checked, > since the possible reference clock source should be kept as configurable > and the clock source should not be limited on the specific IPQ platform, > since the clock source is configurable, the different clock source maybe > required by the different board design. I don't see how this answers anything about our suggestions. Best regards, Krzysztof
On 12/26/2023 9:19 PM, Krzysztof Kozlowski wrote: > On 26/12/2023 14:14, Jie Luo wrote: >> >>>>>> >>>>>> This does not resolve mine and Conor's concerns from previous version. >>>>>> External clocks are defined as clock inputs. >>>>> >>>>> No matter the external or internal reference clock, they are the clock >>>>> source selection for CMN, there are only 48MHZ can be external or >>>>> internal, other clocks have the different clock rate, so the internal >>>>> 48MHZ reference clock can be implied when the >>>>> "qcom,cmn-ref-clock-frequency" is not defined, which is suggested by >>>>> Conor in the previous >>>>> comments. >>>> >>>> I don't think he proposed it, but maybe I missed some message (care to >>>> point me to his message where he agreed on usage of >>>> qcom,cmn-ref-clock-frequency?). I am pretty sure we both stayed on the >>>> same page, that the presence of clocks defines choice of internal clock. >>>> This property should go away. >>> >>> Exactly, I wanted this property to be removed. My suggestion was about >>> defaulting to the internal clock when the "clocks" property did not >>> contain the cmn ref clock. >> >> There are two internal reference clock sources 48MHZ and 96MHZ. > > On which devices? Paste entire picture, not half-baked descriptions. On IPQ9574, the default reference clock source is internal 48MHZ, but the internal 96MHZ is also configurable on IPQ9574. If it imply the internal reference clock used by the combination of the absent of the property and the compatible string, which can't distinguish the internal 48MHZ and internal 96MHZ on ipq9574. Since all the reference clock sources have the different clock rate except for 48MHZ that has internal and external 48MHZ, we just needs to imply the internal 48MHZ used when the property is absent, other clock sources are decided by the frequency value of the property. > >> The 96MHZ is used on ipq5018 currently as i said in the previous >> message, but it is also possible to used on ipq9574 per double checked, >> since the possible reference clock source should be kept as configurable >> and the clock source should not be limited on the specific IPQ platform, >> since the clock source is configurable, the different clock source maybe >> required by the different board design. > > I don't see how this answers anything about our suggestions. The reference clock source can be distinguished by the frequency value as described above. Without limiting the reference clock source with the compatible string, the reference clock sources can be kept configurable on IPQ platform, which makes the MDIO driver code extensible. > > Best regards, > Krzysztof >
On 12/26/2023 9:18 PM, Krzysztof Kozlowski wrote: > On 26/12/2023 14:06, Jie Luo wrote: >> >>> >>> >>>> >>>>> >>>>>> + the platform IPQ50xx/IPQ5332. >>>>> >>>>> So these are valid for all platforms or not? Looks not, but nothing >>>>> narrows the list for other boards. >>>> >>>> i add the limitation on the reg usage for the ipq5332 platform on the >>>> following part "if condition" of this patch, i will update the patch >>>> to narrow down for the other compatibles. >>>> >>>>> >>>>> Anyway, why do you add entries in the middle? LDO was the second, so it >>>>> cannot be now fifth. >>>> >>>> As Rob's suggestion, i move the cmn_blk to second location for >>>> simplifying the limitation description, i checked the upstream dts code, >>>> the LDO is not used currently, so we can move cmn_blk to the second >>>> location here. >>> >>> I cannot find his suggestion in the previous thread. Where did he >>> propose it? >> >> Rob suggested this on the V2 as below. >> " >> Perhaps cmn_blk should come 2nd, so all the variants have the same entry >> indices. Then you can move this to the top level and just say 'minItems: >> 4' here. > > Wasn't this for new devices? What about all existing which have LDO as > the second entry? In the current regs, which includes mdio and one LDO. mdio is the reg address range for all IPQs. one LDO is only for ipq5018. the new added LDO is for ipq5332. the cmn_blk is for ipq9574 and ipq5332. i will update these limitations of dt-bindings in the next patch set. > >>>>>> + qcom,cmn-ref-clock-frequency: >>>>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>>>> + enum: >>>>>> + - 25000000 >>>>>> + - 31250000 >>>>>> + - 40000000 >>>>>> + - 48000000 >>>>>> + - 50000000 >>>>>> + - 96000000 >>>>>> + default: 48000000 >>>>>> + description: | >>>>>> + The reference clock source of CMN PLL block is selectable, the >>>>>> + reference clock source can be from wifi module or the external >>>>>> + xtal, the reference clock frequency 48MHZ can be from internal >>>>>> + wifi or the external xtal, if absent, the internal 48MHZ is used, >>>>>> + if the 48MHZ is specified, which means the external 48Mhz is used. >>>>> >>>>> This does not resolve mine and Conor's concerns from previous version. >>>>> External clocks are defined as clock inputs. >>>> >>>> No matter the external or internal reference clock, they are the clock >>>> source selection for CMN, there are only 48MHZ can be external or >>>> internal, other clocks have the different clock rate, so the internal >>>> 48MHZ reference clock can be implied when the >>>> "qcom,cmn-ref-clock-frequency" is not defined, which is suggested by >>>> Conor in the previous >>>> comments. >>> >>> I don't think he proposed it, but maybe I missed some message (care to >>> point me to his message where he agreed on usage of >>> qcom,cmn-ref-clock-frequency?). I am pretty sure we both stayed on the >>> same page, that the presence of clocks defines choice of internal clock. >>> This property should go away. >> >> Sorry for this confusion. >> Rob said the internal reference source can be decided by the absence of >> the property combined with compatible string, because i said the > > So all your three DT maintainers agree that lack of property for > choosing clock, defines the usage of interrupt source. This is the reference clock source selection of CMN block, which generates the clocks for the Ethernet devices. > > Now we had huge amount of arguments that you do not represent properly > the clock relationships. Still. here is the clock topology. reference clock sources ---> CMN PLL ---> various output clocks the output clocks are provided to the Ethernet devices(such as the qca808x PHY devices). These information is also provided the commit message of the patch <net: mdio: ipq4019: configure CMN PLL clock for ipq5332>. > >> internal 96MHZ is used on ipq5018 currently in the previous message. >> >> per double checked the current IPQ platforms, the internal 96MHZ is also >> possible on ipq9574, and the reference clock source should be kept as >> configurable instead of limited by the compatible string, maybe the >> different reference clock source is acquired in the future, even >> currently it is not used on the special platform for now. >> >> so i update the solution with a little bit of changes. > > You still do not want to implement our suggestions and I don't > understand your arguments. Nothing in above paragraph explains me why > you cannot use clock provider/consumer relationships. Hi Krzysztof, The reference clock source can be registered as the fix clock provider, From the current fix clock provider, the clock rate is useful for the clock consumer, the fix clock rate is used to generate the output clocks by the divider or multiplier. For the CMN block to select reference clock, which is configuring the clock source, we don't know the formula to get the output clock value based on the reference clock value. i also see there is an example in the upstream code, which is same as the CMN block to select the reference clock source. the property "ref-clock-frequency" is defined in the yaml file below. Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml. " ref-clock-frequency: $ref: /schemas/types.yaml#/definitions/uint32 description: Reference clock frequency. " the reference clock source is selected based on the table as below. source code file drivers/net/wireless/ti/wl12xx/main.c " static const struct wl12xx_clock wl12xx_refclock_table[] = { { 19200000, false, WL12XX_REFCLOCK_19 }, { 26000000, false, WL12XX_REFCLOCK_26 }, { 26000000, true, WL12XX_REFCLOCK_26_XTAL }, { 38400000, false, WL12XX_REFCLOCK_38 }, { 38400000, true, WL12XX_REFCLOCK_38_XTAL }, { 52000000, false, WL12XX_REFCLOCK_52 }, { 0, false, 0 } }; " Thanks. > > > Best regards, > Krzysztof >
On 28/12/2023 08:38, Jie Luo wrote: >>> Sorry for this confusion. >>> Rob said the internal reference source can be decided by the absence of >>> the property combined with compatible string, because i said the >> >> So all your three DT maintainers agree that lack of property for >> choosing clock, defines the usage of interrupt source. > > This is the reference clock source selection of CMN block, which > generates the clocks for the Ethernet devices. > >> >> Now we had huge amount of arguments that you do not represent properly >> the clock relationships. Still. > > here is the clock topology. > reference clock sources ---> CMN PLL ---> various output clocks How do you guarantee that these clocks are enabled without proper relationships described in DT? In current and future designs? > > the output clocks are provided to the Ethernet devices(such as the > qca808x PHY devices). > > These information is also provided the commit message of the patch > <net: mdio: ipq4019: configure CMN PLL clock for ipq5332>. > >> >>> internal 96MHZ is used on ipq5018 currently in the previous message. >>> >>> per double checked the current IPQ platforms, the internal 96MHZ is also >>> possible on ipq9574, and the reference clock source should be kept as >>> configurable instead of limited by the compatible string, maybe the >>> different reference clock source is acquired in the future, even >>> currently it is not used on the special platform for now. >>> >>> so i update the solution with a little bit of changes. >> >> You still do not want to implement our suggestions and I don't >> understand your arguments. Nothing in above paragraph explains me why >> you cannot use clock provider/consumer relationships. > > Hi Krzysztof, > > The reference clock source can be registered as the fix clock provider, > From the current fix clock provider, the clock rate is useful for the > clock consumer, the fix clock rate is used to generate the output clocks > by the divider or multiplier. > > For the CMN block to select reference clock, which is configuring the > clock source, we don't know the formula to get the output clock value > based on the reference clock value. I don't understand what does it mean. You do not know how to program CMN block? > > i also see there is an example in the upstream code, which is same as > the CMN block to select the reference clock source. Oh, the old argument. So if there is a bug in the code, you are going for example to implement it as well? > > the property "ref-clock-frequency" is defined in the yaml file below. > Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml. And how does the hardware look like there? It's TI, so how do you even know? Best regards, Krzysztof
On 1/4/2024 3:47 PM, Krzysztof Kozlowski wrote: > On 28/12/2023 08:38, Jie Luo wrote: >>>> Sorry for this confusion. >>>> Rob said the internal reference source can be decided by the absence of >>>> the property combined with compatible string, because i said the >>> >>> So all your three DT maintainers agree that lack of property for >>> choosing clock, defines the usage of interrupt source. >> >> This is the reference clock source selection of CMN block, which >> generates the clocks for the Ethernet devices. >> >>> >>> Now we had huge amount of arguments that you do not represent properly >>> the clock relationships. Still. >> >> here is the clock topology. >> reference clock sources ---> CMN PLL ---> various output clocks > > How do you guarantee that these clocks are enabled without proper > relationships described in DT? In current and future designs? Will update the patch to add the clock relationship in the DT, thanks. > >> >> the output clocks are provided to the Ethernet devices(such as the >> qca808x PHY devices). >> >> These information is also provided the commit message of the patch >> <net: mdio: ipq4019: configure CMN PLL clock for ipq5332>. >> >>> >>>> internal 96MHZ is used on ipq5018 currently in the previous message. >>>> >>>> per double checked the current IPQ platforms, the internal 96MHZ is also >>>> possible on ipq9574, and the reference clock source should be kept as >>>> configurable instead of limited by the compatible string, maybe the >>>> different reference clock source is acquired in the future, even >>>> currently it is not used on the special platform for now. >>>> >>>> so i update the solution with a little bit of changes. >>> >>> You still do not want to implement our suggestions and I don't >>> understand your arguments. Nothing in above paragraph explains me why >>> you cannot use clock provider/consumer relationships. >> >> Hi Krzysztof, >> >> The reference clock source can be registered as the fix clock provider, >> From the current fix clock provider, the clock rate is useful for the >> clock consumer, the fix clock rate is used to generate the output clocks >> by the divider or multiplier. >> >> For the CMN block to select reference clock, which is configuring the >> clock source, we don't know the formula to get the output clock value >> based on the reference clock value. > > I don't understand what does it mean. You do not know how to program CMN > block? The output clock value of CMN block is not related to the clock value of the reference source clock, the output clocks of CMN block are fixed to 25M and 50M, which are provided to the different Ethernet devices, there is no formula for the relationship of input clock value and output clock value of CMN block. > >> >> i also see there is an example in the upstream code, which is same as >> the CMN block to select the reference clock source. > > Oh, the old argument. So if there is a bug in the code, you are going > for example to implement it as well? The reference source clock can be registered as fix clock, and we can get the clock rate of reference source clock with the external or internal flag to distinguish the reference clock source, then program the CMN block corresponding. > >> >> the property "ref-clock-frequency" is defined in the yaml file below. >> Documentation/devicetree/bindings/net/wireless/ti,wlcore.yaml. > > And how does the hardware look like there? It's TI, so how do you even know? According to the driver code and DT description, the example is also for selecting the reference clock source according to the clock value of DT properties. Sure, we can also use the registered fix clock to identify the reference clock source for CMN block. > > > > Best regards, > Krzysztof >
diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml index 3407e909e8a7..205500cb1fd1 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml @@ -18,8 +18,10 @@ properties: - items: - enum: + - qcom,ipq5332-mdio - qcom,ipq6018-mdio - qcom,ipq8074-mdio + - qcom,ipq9574-mdio - const: qcom,ipq4019-mdio "#address-cells": @@ -30,19 +32,76 @@ properties: reg: minItems: 1 - maxItems: 2 - description: - the first Address and length of the register set for the MDIO controller. - the second Address and length of the register for ethernet LDO, this second - address range is only required by the platform IPQ50xx. + maxItems: 5 + description: | + The first address and length of the register set for the MDIO controller, + the optional second address and length of the register is for CMN block, + the optional third, fourth and fifth address and length of the register + for Ethernet LDO, the optional Ethernet LDO address range is required by + the platform IPQ50xx/IPQ5332. + + reg-names: + minItems: 1 + items: + - const: mdio + - const: cmn_blk + - const: eth_ldo1 + - const: eth_ldo2 + - const: eth_ldo3 clocks: + minItems: 1 items: - description: MDIO clock source frequency fixed to 100MHZ + - description: UNIPHY0 AHB clock source frequency fixed to 100MHZ + - description: UNIPHY1 AHB clock source frequency fixed to 100MHZ + - description: UNIPHY0 SYS clock source frequency fixed to 24MHZ + - description: UNIPHY1 SYS clock source frequency fixed to 24MHZ clock-names: + minItems: 1 items: - const: gcc_mdio_ahb_clk + - const: uniphy0_ahb + - const: uniphy1_ahb + - const: uniphy0_sys + - const: uniphy1_sys + + qcom,cmn-ref-clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 25000000 + - 31250000 + - 40000000 + - 48000000 + - 50000000 + - 96000000 + default: 48000000 + description: | + The reference clock source of CMN PLL block is selectable, the + reference clock source can be from wifi module or the external + xtal, the reference clock frequency 48MHZ can be from internal + wifi or the external xtal, if absent, the internal 48MHZ is used, + if the 48MHZ is specified, which means the external 48Mhz is used. + + clock-frequency: + enum: + - 390625 + - 781250 + - 1562500 + - 3125000 + - 6250000 + - 12500000 + default: 390625 + description: | + The MDIO bus clock that must be output by the MDIO bus hardware, + only the listed frequencies above can be supported, other frequency + will cause malfunction. If absent, the default hardware value 0xff + is used, which means the default MDIO clock frequency 390625HZ, The + MDIO clock frequency is MDIO_SYS_CLK/(MDIO_CLK_DIV + 1), the SoC + MDIO_SYS_CLK is fixed to 100MHZ, the MDIO_CLK_DIV is from MDIO control + register, there is higher clock frequency requirement on the normal + working case where the MDIO slave devices support high clock frequency. required: - compatible @@ -59,8 +118,10 @@ allOf: contains: enum: - qcom,ipq5018-mdio + - qcom,ipq5332-mdio - qcom,ipq6018-mdio - qcom,ipq8074-mdio + - qcom,ipq9574-mdio then: required: - clocks @@ -70,6 +131,20 @@ allOf: clocks: false clock-names: false + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-mdio + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + reg-names: + minItems: 4 + unevaluatedProperties: false examples: @@ -100,3 +175,59 @@ examples: reg = <4>; }; }; + + - | + #include <dt-bindings/clock/qcom,ipq5332-gcc.h> + #include <dt-bindings/gpio/gpio.h> + + mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq5332-mdio", + "qcom,ipq4019-mdio"; + + reg = <0x90000 0x64>, + <0x9b000 0x800>, + <0x7a00610 0x4>, + <0x7a10610 0x4>; + + reg-names = "mdio", + "cmn_blk", + "eth_ldo1", + "eth_ldo2"; + + clocks = <&gcc GCC_MDIO_AHB_CLK>, + <&gcc GCC_UNIPHY0_AHB_CLK>, + <&gcc GCC_UNIPHY1_AHB_CLK>, + <&gcc GCC_UNIPHY0_SYS_CLK>, + <&gcc GCC_UNIPHY1_SYS_CLK>; + + clock-names = "gcc_mdio_ahb_clk", + "uniphy0_ahb", + "uniphy1_ahb", + "uniphy0_sys", + "uniphy1_sys"; + + clock-frequency = <6250000>; + reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>; + + qca8kphy0: ethernet-phy@1 { + compatible = "ethernet-phy-id004d.d180"; + reg = <1>; + }; + + qca8kphy1: ethernet-phy@2 { + compatible = "ethernet-phy-id004d.d180"; + reg = <2>; + }; + + qca8kphy2: ethernet-phy@3 { + compatible = "ethernet-phy-id004d.d180"; + reg = <3>; + }; + + qca8kphy3: ethernet-phy@4 { + compatible = "ethernet-phy-id004d.d180"; + reg = <4>; + }; + };
Update the yaml file for the new DTS properties. 1. qcom,cmn-ref-clock-frequency for the CMN PLL source clock select. 2. clock-frequency for MDIO clock frequency config. 3. add uniphy AHB & SYS GCC clocks. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> --- .../bindings/net/qcom,ipq4019-mdio.yaml | 141 +++++++++++++++++- 1 file changed, 136 insertions(+), 5 deletions(-)