From patchwork Thu Jan 4 13:01:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 13511100 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 94E7E24B4F for ; Thu, 4 Jan 2024 13:02:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=bgdev.pl Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=bgdev.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bgdev-pl.20230601.gappssmtp.com header.i=@bgdev-pl.20230601.gappssmtp.com header.b="dH8srkkZ" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-40e35f187b3so213735e9.1 for ; Thu, 04 Jan 2024 05:02:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bgdev-pl.20230601.gappssmtp.com; s=20230601; t=1704373335; x=1704978135; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3E4Vbkb/LrKV7uJsCtqtIqNAbn7WFp6GN2T7jU5w+KA=; b=dH8srkkZC12Yni1cdQmwYzTHLQPkXZNRUh5Opjrh+o80Wt0pEMRfUghmtWh/0N/P29 qvNRDlWe13YKYOQLVhGbYd6/lmRnj60zmPhArYWzhraqy0cMT4WjRiCLrRZ3j1OSvADE c+rtAMqhImveO5kli7DtpD+09Pnv9ogfpf5ErACTwu6qyca5unzBIFRYL147jHbas3zX 6GHlQW3raMYx5J5rV+UN9Ttkc5W7c9HwuLqZwdQoAW2/NYnGmyVxbqlYng+qqABPeCHi kIM3l29YIyi4zAipG58ab1QSwCGrY0CSIwoWX1RLDq3OvEY5H9v+504B9HaOHoi94M7A oSZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704373335; x=1704978135; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3E4Vbkb/LrKV7uJsCtqtIqNAbn7WFp6GN2T7jU5w+KA=; b=FrXcaufMj7u7hVNJfXGP9oUua77HfyTL2Q7kNxRT37dGNALgqCqFM/NYHNMHKgRZJJ 2X9ZBSzEZgZkXKAmwN5hQ6sTYhRQcZDqEhJpGslAOBkWG5IvuZOTt8pNDGChD50qGOWx VTGl4jQWh9sYEAZKwnWKrCNpC+CVfNKLBuh3/Tv0o+90nm2DW4DVBNp3fOJYMdMzakTB cGZq1+nLlU9UFGBiCIWZOgGopxmFZp66NO9lT7Xf4hWQvz1HvvPVw4gxQ8Wh5QatUcLI rpChCJ7M1QZ6l82qVJuTgUm0jBGDmiLOgF0HiRoY1/lJqAznkt2c43yb16GUHdNy7SgC qHWQ== X-Gm-Message-State: AOJu0YyV085mIYb0TLBu8bHcoNabkXBWSWItVZ6K9vKuITOm2LR7lwk4 dP23Sw/0x7MKCjZgwUU8P8qmmGgIMt8fLg== X-Google-Smtp-Source: AGHT+IHHXVpRs7QMqS9kg1ok0JTc8TTEP2DuD/O7GN8bhaZdGEhV9MHAS2mTz+G8GWP6ubM9PTmRyw== X-Received: by 2002:a05:600c:300b:b0:40d:f9c8:887f with SMTP id j11-20020a05600c300b00b0040df9c8887fmr331173wmh.51.1704373334899; Thu, 04 Jan 2024 05:02:14 -0800 (PST) Received: from brgl-uxlite.home ([2a01:cb1d:334:ac00:5b69:3768:8459:8fee]) by smtp.gmail.com with ESMTPSA id w5-20020a5d5445000000b0033660f75d08sm32887387wrv.116.2024.01.04.05.02.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 05:02:14 -0800 (PST) From: Bartosz Golaszewski To: Kalle Valo , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Catalin Marinas , Will Deacon , Bjorn Helgaas , Heiko Stuebner , Jernej Skrabec , Chris Morgan , Linus Walleij , Geert Uytterhoeven , Arnd Bergmann , Neil Armstrong , =?utf-8?q?N=C3=ADcolas_F_=2E_R_?= =?utf-8?q?=2E_A_=2E_Prado?= , Marek Szyprowski , Peng Fan , Robert Richter , Dan Williams , Jonathan Cameron , Terry Bowman , Kuppuswamy Sathyanarayanan , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Huacai Chen , Alex Elder , Srini Kandagatla , Greg Kroah-Hartman Cc: linux-wireless@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, Bartosz Golaszewski Subject: [RFC 8/9] PCI/pwrseq: add a pwrseq driver for QCA6390 Date: Thu, 4 Jan 2024 14:01:22 +0100 Message-Id: <20240104130123.37115-9-brgl@bgdev.pl> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240104130123.37115-1-brgl@bgdev.pl> References: <20240104130123.37115-1-brgl@bgdev.pl> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Bartosz Golaszewski Add a PCIe power sequencing driver that's capable of correctly powering up the ath11k module on QCA6390 using the PCIe pwrseq functionality. Signed-off-by: Bartosz Golaszewski --- drivers/pci/pcie/pwrseq/Kconfig | 11 + drivers/pci/pcie/pwrseq/Makefile | 1 + drivers/pci/pcie/pwrseq/pcie-pwrseq-qca6390.c | 197 ++++++++++++++++++ 3 files changed, 209 insertions(+) create mode 100644 drivers/pci/pcie/pwrseq/pcie-pwrseq-qca6390.c diff --git a/drivers/pci/pcie/pwrseq/Kconfig b/drivers/pci/pcie/pwrseq/Kconfig index 010e31f432c9..f9fe555b8506 100644 --- a/drivers/pci/pcie/pwrseq/Kconfig +++ b/drivers/pci/pcie/pwrseq/Kconfig @@ -6,3 +6,14 @@ menuconfig PCIE_PWRSEQ help Say yes here to enable support for PCIe power sequencing drivers. + +if PCIE_PWRSEQ + +config PCIE_PWRSEQ_QCA6390 + tristate "PCIe Power Sequencing driver for QCA6390" + depends on ARCH_QCOM || COMPILE_TEST + help + Enable support for the PCIe power sequencing driver for the + ath11k module of the QCA6390 WLAN/BT chip. + +endif diff --git a/drivers/pci/pcie/pwrseq/Makefile b/drivers/pci/pcie/pwrseq/Makefile index da99566594f6..da3e02063404 100644 --- a/drivers/pci/pcie/pwrseq/Makefile +++ b/drivers/pci/pcie/pwrseq/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_PWRSEQ) += pwrseq.o +obj-$(CONFIG_PCIE_PWRSEQ_QCA6390) += pcie-pwrseq-qca6390.o diff --git a/drivers/pci/pcie/pwrseq/pcie-pwrseq-qca6390.c b/drivers/pci/pcie/pwrseq/pcie-pwrseq-qca6390.c new file mode 100644 index 000000000000..e9fddbb642fe --- /dev/null +++ b/drivers/pci/pcie/pwrseq/pcie-pwrseq-qca6390.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2023 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct pcie_pwrseq_qca6390_vreg { + const char *name; + unsigned int load_uA; +}; + +struct pcie_pwrseq_qca6390_pdata { + struct pcie_pwrseq_qca6390_vreg *vregs; + size_t num_vregs; + unsigned int delay_msec; +}; + +struct pcie_pwrseq_qca6390_ctx { + struct pcie_pwrseq pwrseq; + const struct pcie_pwrseq_qca6390_pdata *pdata; + struct regulator_bulk_data *regs; + struct gpio_descs *en_gpios; + unsigned long *en_gpios_values; +}; + +static struct pcie_pwrseq_qca6390_vreg pcie_pwrseq_qca6390_vregs[] = { + { + .name = "vddpmu", + .load_uA = 1250000, + }, + { + .name = "vddpcie1", + .load_uA = 35000, + }, + { + .name = "vddpcie2", + .load_uA = 15000, + }, +}; + +static struct pcie_pwrseq_qca6390_pdata pcie_pwrseq_qca6390_of_data = { + .vregs = pcie_pwrseq_qca6390_vregs, + .num_vregs = ARRAY_SIZE(pcie_pwrseq_qca6390_vregs), + .delay_msec = 16, +}; + +static int pcie_pwrseq_qca6390_power_on(struct pcie_pwrseq_qca6390_ctx *ctx) +{ + int ret; + + ret = regulator_bulk_enable(ctx->pdata->num_vregs, ctx->regs); + if (ret) + return ret; + + bitmap_fill(ctx->en_gpios_values, ctx->en_gpios->ndescs); + + ret = gpiod_set_array_value_cansleep(ctx->en_gpios->ndescs, + ctx->en_gpios->desc, + ctx->en_gpios->info, + ctx->en_gpios_values); + if (ret) { + regulator_bulk_disable(ctx->pdata->num_vregs, ctx->regs); + return ret; + } + + if (ctx->pdata->delay_msec) + msleep(ctx->pdata->delay_msec); + + return 0; +} + +static int pcie_pwrseq_qca6390_power_off(struct pcie_pwrseq_qca6390_ctx *ctx) +{ + int ret; + + bitmap_zero(ctx->en_gpios_values, ctx->en_gpios->ndescs); + + ret = gpiod_set_array_value_cansleep(ctx->en_gpios->ndescs, + ctx->en_gpios->desc, + ctx->en_gpios->info, + ctx->en_gpios_values); + if (ret) + return ret; + + return regulator_bulk_disable(ctx->pdata->num_vregs, ctx->regs); +} + +static void devm_pcie_pwrseq_qca6390_power_off(void *data) +{ + struct pcie_pwrseq_qca6390_ctx *ctx = data; + + pcie_pwrseq_qca6390_power_off(ctx); +} + +static int pcie_pwrseq_qca6309_probe(struct platform_device *pdev) +{ + struct pcie_pwrseq_qca6390_ctx *ctx; + struct device *dev = &pdev->dev; + int ret, i; + + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->pdata = of_device_get_match_data(dev); + if (!ctx->pdata) + return dev_err_probe(dev, -ENODEV, + "Failed to obtain platform data\n"); + + if (ctx->pdata->vregs) { + ctx->regs = devm_kcalloc(dev, ctx->pdata->num_vregs, + sizeof(*ctx->regs), GFP_KERNEL); + if (!ctx->regs) + return -ENOMEM; + + for (i = 0; i < ctx->pdata->num_vregs; i++) + ctx->regs[i].supply = ctx->pdata->vregs[i].name; + + ret = devm_regulator_bulk_get(dev, ctx->pdata->num_vregs, + ctx->regs); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to get all regulators\n"); + + for (i = 0; i < ctx->pdata->num_vregs; i++) { + ret = regulator_set_load(ctx->regs[i].consumer, + ctx->pdata->vregs[i].load_uA); + if (ret) + return dev_err_probe(dev, ret, + "Failed to set vreg load\n"); + } + } + + ctx->en_gpios = devm_gpiod_get_array_optional(dev, "enable", + GPIOD_OUT_LOW); + if (IS_ERR(ctx->en_gpios)) + return dev_err_probe(dev, PTR_ERR(ctx->en_gpios), + "Failed to get enable GPIOs\n"); + + ctx->en_gpios_values = devm_bitmap_zalloc(dev, ctx->en_gpios->ndescs, + GFP_KERNEL); + if (!ctx->en_gpios_values) + return -ENOMEM; + + ret = pcie_pwrseq_qca6390_power_on(ctx); + if (ret) + return dev_err_probe(dev, ret, + "Failed to power on the device\n"); + + ret = devm_add_action_or_reset(dev, devm_pcie_pwrseq_qca6390_power_off, + ctx); + if (ret) + return ret; + + ctx->pwrseq.dev = dev; + + ret = devm_pcie_pwrseq_device_enable(dev, &ctx->pwrseq); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register the pwrseq wrapper\n"); + + return 0; +} + +static const struct of_device_id pcie_pwrseq_qca6309_of_match[] = { + { + .compatible = "pci17cb,1101", + .data = &pcie_pwrseq_qca6390_of_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, pcie_pwrseq_qca6309_of_match); + +static struct platform_driver pcie_pwrseq_qca6309_driver = { + .driver = { + .name = "pcie-pwrseq-qca6390", + .of_match_table = pcie_pwrseq_qca6309_of_match, + }, + .probe = pcie_pwrseq_qca6309_probe, +}; +module_platform_driver(pcie_pwrseq_qca6309_driver); + +MODULE_AUTHOR("Bartosz Golaszewski "); +MODULE_DESCRIPTION("PCIe Power Sequencing module for QCA6390"); +MODULE_LICENSE("GPL");