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[178.235.179.81]) by smtp.gmail.com with ESMTPSA id bs18-20020a170906d1d200b00a2808ee8ab1sm3892978ejb.150.2024.01.08.04.32.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 04:32:58 -0800 (PST) From: Konrad Dybcio Date: Mon, 08 Jan 2024 13:32:33 +0100 Subject: [PATCH 16/18] clk: qcom: videocc-sm8350: Set delay for Venus CLK resets Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240105-topic-venus_reset-v1-16-981c7a624855@linaro.org> References: <20240105-topic-venus_reset-v1-0-981c7a624855@linaro.org> In-Reply-To: <20240105-topic-venus_reset-v1-0-981c7a624855@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Philipp Zabel Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Bryan O'Donoghue , Dikshita Agarwal , Vikash Garodia , Konrad Dybcio , Manivannan Sadhasivam X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704717148; l=1051; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=AdVr2Vo+gKTKy1lOaf9tWddLXbATgKX8KeFGJ/zSkw0=; b=wIi+5K4T1WvVGh/iD46R12XlclSx3BIGbgYBU44VJXW0beQIKu4GsbVtmqKDbAhCc12MiGkwJ tByulC6Qr8fBWo03C+KT6ixJj+rF1wnViPqH+f7CUr+dGrPvwcpcw0/ X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Some Venus resets may require more time when toggling. Describe that. Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/videocc-sm8350.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8350.c b/drivers/clk/qcom/videocc-sm8350.c index 7246f3c99492..8db2bb995558 100644 --- a/drivers/clk/qcom/videocc-sm8350.c +++ b/drivers/clk/qcom/videocc-sm8350.c @@ -488,10 +488,10 @@ static struct clk_regmap *video_cc_sm8350_clocks[] = { static const struct qcom_reset_map video_cc_sm8350_resets[] = { [VIDEO_CC_CVP_INTERFACE_BCR] = { 0xe54 }, [VIDEO_CC_CVP_MVS0_BCR] = { 0xd14 }, - [VIDEO_CC_MVS0C_CLK_ARES] = { 0xc34, 2 }, + [VIDEO_CC_MVS0C_CLK_ARES] = { .reg = 0xc34, .bit = 2, .udelay = 400 }, [VIDEO_CC_CVP_MVS0C_BCR] = { 0xbf4 }, [VIDEO_CC_CVP_MVS1_BCR] = { 0xd94 }, - [VIDEO_CC_MVS1C_CLK_ARES] = { 0xcd4, 2 }, + [VIDEO_CC_MVS1C_CLK_ARES] = { .reg = 0xcd4, .bit = 2, .udelay = 400 }, [VIDEO_CC_CVP_MVS1C_BCR] = { 0xc94 }, };