From patchwork Sun Jan 21 22:33:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marijn Suijten X-Patchwork-Id: 13524689 Received: from relay01.th.seeweb.it (relay01.th.seeweb.it [5.144.164.162]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09B9D383B5; Sun, 21 Jan 2024 22:33:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=5.144.164.162 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705876426; cv=none; b=tzfkIgvaQ0hkLyQqQUKCy4rDbgo9gOQGW7irnxkPUF/oqA6FF4020TvkPvh9sMX39WcG9AFUw8Fv5o4I9+GuYXa06sgPj2kCbH5iB49tL6LIw70ZYr0w8LKTSIeXelC+zPoonouHmcNwbdGgRyDkbZem/h0HaNmtokL9aAFxwiI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705876426; c=relaxed/simple; bh=Ka0suA2f6Mht4+t9XWWJHrO4gwspsyTwEIQwdjMFPoc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=m5ROh4ec+oxRymrZ1qku5+kgPhwiUcje/Hy+hqTvt+SiRBKkz+Da7RlDy/BTOHtgf2JgvKEhcWnglGE+gH7PpDgK3FFU12uE9tlihYStbVJXs1rNcvsjCEO4s7d4BNssH49vv4hJklbE0MqShVTJPKg5yolrjnCQCN7esiRViIQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=somainline.org; spf=pass smtp.mailfrom=somainline.org; arc=none smtp.client-ip=5.144.164.162 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=somainline.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=somainline.org Received: from Marijn-Arch-PC.localdomain (94-211-6-86.cable.dynamic.v4.ziggo.nl [94.211.6.86]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id 7436720385; Sun, 21 Jan 2024 23:33:42 +0100 (CET) From: Marijn Suijten Date: Sun, 21 Jan 2024 23:33:41 +0100 Subject: [PATCH v2 4/6] arm64: dts: qcom: msm8976: Declare and use SDC1 pins Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240121-msm8976-dt-v2-4-7b186a02dc72@somainline.org> References: <20240121-msm8976-dt-v2-0-7b186a02dc72@somainline.org> In-Reply-To: <20240121-msm8976-dt-v2-0-7b186a02dc72@somainline.org> To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Luca Weiss , Adam Skladowski , Konrad Dybcio , Martin Botka , Jami Kettunen , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Marijn Suijten X-Mailer: b4 0.12.4 Add the pinctrl states for SDC1 and use them on sdhc_1. Signed-off-by: Marijn Suijten --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 55 +++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index d2bb1ada361a..1d06f9b8a0f1 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -669,6 +669,56 @@ tlmm: pinctrl@1000000 { interrupt-controller; #interrupt-cells = <2>; + sdc1_off_state: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_on_state: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + spi1_default: spi0-default-state { spi-pins { pins = "gpio0", "gpio1", "gpio3"; @@ -840,6 +890,11 @@ sdhc_1: mmc@7824900 { <&gcc GCC_SDCC1_APPS_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "core", "xo"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on_state>; + pinctrl-1 = <&sdc1_off_state>; + status = "disabled"; };