| Message ID | 20240122-topic-sm8550-upstream-pcie-its-v2-1-b3398d86d1f1@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v2] arm64: dts: qcom: sm8550: Use GIC-ITS for PCIe0 and PCIe1 | expand |
On Mon, 22 Jan 2024 16:38:17 +0100, Neil Armstrong wrote: > Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs > received from endpoint devices to the CPU using GIC-ITS MSI controller. > Add support for it. > > The GIC-ITS MSI implementation provides an advantage over internal MSI > implementation using Locality-specific Peripheral Interrupts (LPI) that > would allow MSIs to be targeted for each CPU core. > > [...] Applied, thanks! [1/1] arm64: dts: qcom: sm8550: Use GIC-ITS for PCIe0 and PCIe1 commit: 114990ce3edfd059648889f978cbdc83447b305b Best regards,
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ee1ba5a8c8fc..9860bda3be1d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1742,6 +1742,9 @@ pcie0: pcie@1c00000 { <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; + /* Entries are reversed due to the unusual ITS DeviceID encoding */ + msi-map = <0x0 &gic_its 0x1401 0x1>, + <0x100 &gic_its 0x1400 0x1>; iommu-map = <0x0 &apps_smmu 0x1400 0x1>, <0x100 &apps_smmu 0x1401 0x1>; @@ -1838,6 +1841,9 @@ pcie1: pcie@1c08000 { <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; interconnect-names = "pcie-mem", "cpu-pcie"; + /* Entries are reversed due to the unusual ITS DeviceID encoding */ + msi-map = <0x0 &gic_its 0x1481 0x1>, + <0x100 &gic_its 0x1480 0x1>; iommu-map = <0x0 &apps_smmu 0x1480 0x1>, <0x100 &apps_smmu 0x1481 0x1>;
Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs received from endpoint devices to the CPU using GIC-ITS MSI controller. Add support for it. The GIC-ITS MSI implementation provides an advantage over internal MSI implementation using Locality-specific Peripheral Interrupts (LPI) that would allow MSIs to be targeted for each CPU core. Like SM8450, the IDs are swapped, but works fine on PCIe0 and PCIe1. WiFi PCIe Device on SM8550-QRD using GIC-ITS: 218: 0 4 0 0 0 0 0 0 ITS-MSI 524288 Edge bhi 219: 0 0 5 0 0 0 0 0 ITS-MSI 524289 Edge mhi 220: 0 0 0 33 0 0 0 0 ITS-MSI 524290 Edge mhi 221: 0 0 0 0 3 0 0 0 ITS-MSI 524291 Edge ce0 222: 0 0 0 0 0 1 0 0 ITS-MSI 524292 Edge ce1 223: 0 0 0 0 0 0 38 0 ITS-MSI 524293 Edge ce2 224: 0 0 0 0 0 0 0 31 ITS-MSI 524294 Edge ce3 225: 0 0 0 0 0 0 0 0 ITS-MSI 524295 Edge ce5 226: 0 0 0 0 0 0 0 0 ITS-MSI 524296 Edge DP_EXT_IRQ 227: 0 0 0 0 0 0 0 0 ITS-MSI 524297 Edge DP_EXT_IRQ 228: 0 0 0 0 0 0 0 0 ITS-MSI 524298 Edge DP_EXT_IRQ 229: 0 0 0 0 0 0 0 0 ITS-MSI 524299 Edge DP_EXT_IRQ 230: 0 0 0 0 0 0 0 0 ITS-MSI 524300 Edge DP_EXT_IRQ 231: 0 0 0 0 0 0 0 0 ITS-MSI 524301 Edge DP_EXT_IRQ 232: 0 0 0 0 0 0 0 0 ITS-MSI 524302 Edge DP_EXT_IRQ NVMe in SM8550-HDK M.2 Slot using GIC-ITS: 212: 0 0 22 0 0 0 0 0 ITS-MSI 134742016 Edge nvme0q0 213: 133098 0 0 0 0 0 0 0 ITS-MSI 134742017 Edge nvme0q1 214: 0 139450 0 0 0 0 0 0 ITS-MSI 134742018 Edge nvme0q2 215: 0 0 139476 0 0 0 0 0 ITS-MSI 134742019 Edge nvme0q3 216: 0 0 0 69767 0 0 0 0 ITS-MSI 134742020 Edge nvme0q4 217: 0 0 0 0 80368 0 0 0 ITS-MSI 134742021 Edge nvme0q5 218: 0 0 0 0 0 77315 0 0 ITS-MSI 134742022 Edge nvme0q6 219: 0 0 0 0 0 0 73022 0 ITS-MSI 134742023 Edge nvme0q7 220: 0 0 0 0 0 0 0 329993 ITS-MSI 134742024 Edge nvme0q8 Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Changes in v2: - fixed commit msg - Link to v1: https://lore.kernel.org/r/20240122-topic-sm8550-upstream-pcie-its-v1-1-aff5d0d7d6dd@linaro.org --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) --- base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d change-id: 20240122-topic-sm8550-upstream-pcie-its-06f4b61dfe9d Best regards,