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Tue, 23 Jan 2024 23:37:56 -0800 (PST) Received: from [127.0.1.1] ([117.217.189.109]) by smtp.gmail.com with ESMTPSA id t3-20020a170902b20300b001d726d9f591sm7386982plr.196.2024.01.23.23.37.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 23:37:56 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 24 Jan 2024 13:06:42 +0530 Subject: [PATCH 14/14] arm64: dts: qcom: sa8775p: Drop PCIE_AUX_CLK from pcie_phy nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240124-pcie-aux-clk-fix-v1-14-d8a4852b6ba6@linaro.org> References: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> In-Reply-To: <20240124-pcie-aux-clk-fix-v1-0-d8a4852b6ba6@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2114; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=AV0AQVKEuKDRIth7QZV7qLd22LfBtighoMaozbvkXAg=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlsL4Fhhiw+ROelMo4VRCj1+Kx7T9cS2AThYZkc DknKia3ul+JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZbC+BQAKCRBVnxHm/pHO 9bthCACRQjvyFRVJy3hTYxwCqypCA959YVl640Spi+/5TQUxSwUS5HOza3ZjI6ZCE6ZAV0awrPp Ma31wRRoKSgL0QcvLroRMpG1W5pN5E1/CJq/7joMoTGV0Gytn1w4fGIB6/kSXkiPqOPMbNMCVFF Ngelg4E2chxrplR8oOICcl/mKuhw922a3poiiA+oCWhEqfmYWYYtsF2apAswH19tebHdmBaK1SZ R6CuqE5X5TaD+C9YLOpC2/R0IwNZhXa5IF44UqN+Z2XWohLPbBrvLIpcPH81pLIQtrGgFaeeM8N gbnY/iNcmWsx9j3N5iilOXhEMCW5MWYCIzifzYfgmlKRHqBf X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is only required by the PCIe controller. Hence drop it from pcie_phy nodes. While at it, let's also rename "phy_aux" clock to "aux" clock and move it to first entry to maintain uniformity with other SoCs. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index a7eaca33d326..b99626c52800 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3590,16 +3590,15 @@ pcie0_phy: phy@1c04000 { compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; reg = <0x0 0x1c04000 0x0 0x2000>; - clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>, - <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, - <&gcc GCC_PCIE_0_PHY_AUX_CLK>; + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", - "pipediv2", "phy_aux"; + "pipediv2"; assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>; @@ -3690,16 +3689,15 @@ pcie1_phy: phy@1c14000 { compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; reg = <0x0 0x1c14000 0x0 0x4000>; - clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK>, - <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, - <&gcc GCC_PCIE_1_PHY_AUX_CLK>; + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", - "pipediv2", "phy_aux"; + "pipediv2"; assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; assigned-clock-rates = <100000000>;