@@ -418,6 +418,12 @@ usb2: usb@70f8800 {
<&gcc GCC_USB1_MOCK_UTMI_CLK>;
assigned-clock-rates = <133330000>,
<24000000>;
+
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy";
+
resets = <&gcc GCC_USB1_BCR>;
status = "disabled";
@@ -630,6 +636,13 @@ usb3: usb@8af8800 {
<133330000>,
<24000000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
+
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
@@ -627,6 +627,13 @@ usb_0: usb@8af8800 {
<133330000>,
<19200000>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
+
power-domains = <&gcc USB0_GDSC>;
resets = <&gcc GCC_USB0_BCR>;
@@ -669,6 +676,13 @@ usb_1: usb@8cf8800 {
<133330000>,
<19200000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
+
power-domains = <&gcc USB1_GDSC>;
resets = <&gcc GCC_USB1_BCR>;
@@ -1160,9 +1160,12 @@ usb3: usb@70f8800 {
#size-cells = <1>;
ranges;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq";
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,
@@ -3408,8 +3408,12 @@ usb2: usb@76f8800 {
#size-cells = <1>;
ranges;
- interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "hs_phy_irq";
clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
<&gcc GCC_USB20_MASTER_CLK>,
@@ -2132,9 +2132,12 @@ usb3: usb@a8f8800 {
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <120000000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq";
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "ss_phy_irq";
power-domains = <&gcc USB_30_GDSC>;
@@ -1281,9 +1281,14 @@ usb3: usb@a8f8800 {
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <120000000>;
- interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq";
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB_30_GDSC>;
qcom,select-utmi-as-pipe-clk;
@@ -1463,8 +1468,12 @@ usb2: usb@c2f8800 {
<&gcc GCC_USB20_MASTER_CLK>;
assigned-clock-rates = <19200000>, <60000000>;
- interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq";
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "hs_phy_irq";
qcom,select-utmi-as-pipe-clk;
@@ -1586,9 +1586,14 @@ usb: usb@4ef8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <66666667>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq";
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "hs_phy_irq",
+ "ss_phy_irq";
resets = <&gcc GCC_USB30_PRIM_BCR>;
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
@@ -1185,9 +1185,14 @@ usb3: usb@4ef8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <66666667>;
- interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq";
+ interrupt-names = "pwr_event",
+ "qusb2_phy",
+ "hs_phy_irq",
+ "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
qcom,select-utmi-as-pipe-clk;
On several QUSB2 Targets, the hs_phy_irq mentioned is actually qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq to qusb2_phy for such targets. In actuality, the hs_phy_irq is also present in these targets, but kept in for debug purposes in hw test environments. This is not triggered by default and its functionality is mutually exclusive to that of qusb2_phy interrupt. Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets. Add missing ss_phy_irq on some targets which allows for remote wakeup to work on a Super Speed link. Also modify order of interrupts in accordance to bindings update. Since driver looks up for interrupts by name and not by index, it is safe to modify order of these interrupts in the DT. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 13 +++++++++++++ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/qcom/msm8953.dtsi | 7 +++++-- arch/arm64/boot/dts/qcom/msm8996.dtsi | 8 ++++++-- arch/arm64/boot/dts/qcom/msm8998.dtsi | 7 +++++-- arch/arm64/boot/dts/qcom/sdm630.dtsi | 17 +++++++++++++---- arch/arm64/boot/dts/qcom/sm6115.dtsi | 9 +++++++-- arch/arm64/boot/dts/qcom/sm6125.dtsi | 9 +++++++-- 8 files changed, 70 insertions(+), 14 deletions(-)