From patchwork Thu Feb 1 21:05:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 13541813 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6C573F8DF; Thu, 1 Feb 2024 21:06:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706821566; cv=none; b=suBS68AlOtPXr7Hxu1KxlGY+J9UAEkKTr4FwQUIUv1mzQKeR8OaGZV/3XBI8mHkHS0bctqGKnZZB9xhenjubqpFESYjv1MokrQTV0qBBZFR1hpQbtzHOq4vpwXxGYgwiI75/ckq5lFBE6eWeJD2HGPGV3Jxwtv4lnk660UTwDMc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706821566; c=relaxed/simple; bh=sqsUTzCm3DyF3ATsBk1uykJ4lTtBTpOapAMVHOoXU/0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IocZT5Z8zJW9cV1hM3Q5wMb00n3URsqeFSzR4WqxUHP61d6sXPgIi+zMhkNVh4UhdjcuUaA/ZOwIxHSXaORnSgZSzz45PcFDJQXvvxlX7XqDveglqqtzdSfXWlbKIJ5DmE15AhyyaQXkEQztLa9MWLT5U2cFSMJV06zSZQ1ECxs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=IcOPEvCs; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="IcOPEvCs" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 411DdMV9004884; Thu, 1 Feb 2024 21:05:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type; s=qcppdkim1; bh=H2KKXBWGzp3tzNYDVi9E wGdsh+1WRKXO9OPhqyU86f0=; b=IcOPEvCsW33jIdHuzenjMwu3F0NZ8hz/ltaI OX2eLHzruhVj1nTEipPcbgmenE3lq4oKqWOFVy6McsrkHjXX5ehIJwnPpgEgdwjj XtfqKVqKPDKK/aoFPK+GVCRnbnaA75Cg6pCnxKEqROkFGd3IMfvqhnSvAaD2Lh7p l/fySbG0eg9TWqJscG3dXSNIektXzd1eONfTsFt23rgcPN2NTR/Cgl321H2e7Qtt jTNLfIwEvDcL6ZEXbz4x5ylWxzAgKTMhC9QzLlV9l5SJi2SD8cCeeX7lExaWirfO KKDptBasHiILuVUr08hce3HtAAzaxpnniS3QFW88VSQyNo/U7g== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vyvb5kd98-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 01 Feb 2024 21:05:41 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 411L5eRE028596 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 1 Feb 2024 21:05:40 GMT Received: from hu-c-gdjako-lv.qualcomm.com (10.49.16.6) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 1 Feb 2024 13:05:39 -0800 From: Georgi Djakov To: , , , , , , CC: , , , , , , , , , , , Subject: [PATCH v4 02/10] dt-bindings: iommu: Add Qualcomm TBU bindings Date: Thu, 1 Feb 2024 13:05:21 -0800 Message-ID: <20240201210529.7728-3-quic_c_gdjako@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240201210529.7728-1-quic_c_gdjako@quicinc.com> References: <20240201210529.7728-1-quic_c_gdjako@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: F5gosPsvU2vjIbO856RjwRZtgHP5wBa5 X-Proofpoint-ORIG-GUID: F5gosPsvU2vjIbO856RjwRZtgHP5wBa5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-01_06,2024-01-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 spamscore=0 clxscore=1015 impostorscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401190000 definitions=main-2402010163 The "apps_smmu" on the Qualcomm sdm845 platform is an implementation of the SMMU-500, that consists of a single TCU (Translation Control Unit) and multiple TBUs (Translation Buffer Units). The TCU is already being described in the ARM SMMU schema and now we have also a common schema for TBUs. The TBUs on Qualcomm platforms have some additional hardware resources that need to be described in the schema. Create a vendor-specific TBU schema to include all the needed resources like clocks, power domains and interconnects. Signed-off-by: Georgi Djakov --- .../devicetree/bindings/iommu/arm,smmu.yaml | 10 +++ .../bindings/iommu/qcom,qsmmuv500-tbu.yaml | 71 +++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index ba3237023b39..537e6a2fc02b 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -326,6 +326,16 @@ allOf: through the TCU's programming interface. - description: bus clock required for the smmu ptw + - if: + properties: + compatible: + contains: + const: qcom,sdm845-smmu-500 + then: + patternProperties: + "^tbu@[0-9a-f]+$": + $ref: qcom,qsmmuv500-tbu.yaml# + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml new file mode 100644 index 000000000000..0e86e1c42133 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/qcom,qsmmuv500-tbu.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/qcom,qsmmuv500-tbu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TBU (Translation Buffer Unit) + +maintainers: + - Georgi Djakov + +description: + The Qualcomm SMMU500 implementation consists of TCU and TBU. The TBU contains + a Translation Lookaside Buffer (TLB) that caches page tables. TBUs provides + debug features to trace and trigger debug transactions. There are multiple TBU + instances with each client core. + +allOf: + - $ref: tbu-common.yaml# + +properties: + compatible: + const: qcom,qsmmuv500-tbu + + clocks: + maxItems: 1 + + interconnects: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - stream-id-range + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + iommu@15000000 { + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; + reg = <0x15000000 0x80000>; + ranges = <0 0 0 0 0xffffffff>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + ; + #address-cells = <2>; + #size-cells = <2>; + + tbu@150e1000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x0 0x150e1000 0x0 0x1000>; + clocks = <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + interconnects = <&system_noc MASTER_GNOC_SNOC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_IMEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + power-domains = <&gcc HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC>; + stream-id-range = <0x1c00 0x400>; + }; + }; +...