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a=openpgp-sha256; l=1737; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=8a+0oyI0cSJoqWk2V6P5ZLmO6u2tJ1UClYhfKKZ2QWw=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlvJGciN/Y0zChE5M99t5u9KSV9M2KE/HUNCrvm er3fnw8mOGJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZbyRnAAKCRBVnxHm/pHO 9S1nB/4jumZoFbgNps6BZOB3a0lMhegz7WtIlzbRJv+6L1+sIUWkv2tHHcWN5uABhRb9v4ObLcp H328Xl2mbuZZDJFZmaNqd22ihNpYSZ1yj5+fIsAwXXw6PGjKuunjkZs/dv7tQRD61dDr9I/jyec W0mh4Iu1xSe/g6Qo0c5ODfo6SWOcl8y17Mo947xnafjV8URXtcZf+tUrKgDHKgDbc92UK88zBSK a5xvY0Mu1G1/Cj5NYsq2JJ3M0pJgPw0k7RxzgD7dR97Li86IjCxVfO8inkLlo5KZjXpY+ROWIGv oFDw78TWDPlJ0PCuqMTdcG6iCHi9rkpSyifMG3nDQMhOnYFc X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 Make use of the "bridge_d3_capable" flag to specify the D3 capability to the PCI core so that the D3 support (in turn runtime PM) will be enabled for the PCI bridges. Currently, only for the recent bridges with PID "0x0110", this flag is set as a fixup. Because, there is no guarantee that the older bridges will support D3. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 10f2d0bb86be..a6ae78d2ce92 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1649,6 +1649,11 @@ static void qcom_fixup_class(struct pci_dev *dev) { dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; } + +static void qcom_fixup_bridge_d3_capability(struct pci_dev *dev) +{ + dev->bridge_d3_capable = true; +} DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class); @@ -1656,6 +1661,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0110, qcom_fixup_bridge_d3_capability); static const struct dev_pm_ops qcom_pcie_pm_ops = { NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_pcie_suspend_noirq, qcom_pcie_resume_noirq)