| Message ID | 20240208062836.19767-6-quic_tdas@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add updates for clock controllers to support QCM6490 | expand |
On Thu, 8 Feb 2024 at 08:29, Taniya Das <quic_tdas@quicinc.com> wrote: > > Certain clocks are not accessible on QCM6490-IDP and QCS6490-RB3GEN2 boards > thus require them to be marked protected. > > Also disable the LPASS nodes which are not to be used. > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 54 +++++++++++++++++++- > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 50 +++++++++++++++++- > 2 files changed, 102 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > index 03e97e27d16d..425e4b87490b 100644 > --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: BSD-3-Clause > /* > - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. > */ > > /dts-v1/; > @@ -415,6 +415,58 @@ > }; > }; > > +&gcc { > + protected-clocks = <GCC_AGGRE_NOC_PCIE_1_AXI_CLK> ,<GCC_PCIE_1_AUX_CLK>, > + <GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>, > + <GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, > + <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>, > + <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>, > + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, > + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, > + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, > + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, > + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, > + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, > + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, > + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, > + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, > + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, > + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, > + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; This looks like a huge variety of clocks. Are they really not accessible or are you trying to make Linux stay away from all those clocks to keep bootloader settings? > +}; > + > +&lpasscc { > + status = "disabled"; > +}; > + > +&lpass_audiocc { > + qcom,adsp-skip-pll; > + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, > + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, > + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, > + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, > + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, > + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, > + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; This almost looks like a separate compatible. > + /delete-property/ power-domains; > +}; > + > +&lpass_aon { > + status = "disabled"; Should this be "reserved", controlled by ADSP? See how this was implemented in sc7180.dtsi / sc7180-trogdor.dtsi. Please consider inverting the logic. Generic ADSP implementation should be present in sc7280.dtsi and then the non-default ChromeOS implementation should be a part of sc7280-chrome-common.dtsi. > +}; > + > +&lpass_core { > + status = "disabled"; > +}; > + > +&lpass_hm { > + status = "disabled"; > +}; > + > &qupv3_id_0 { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > index 8bb7d13d85f6..1398b84634c3 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: BSD-3-Clause > /* > - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. > */ > > /dts-v1/; > @@ -413,6 +413,54 @@ > }; > }; > > +&gcc { > + protected-clocks = <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, > + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, > + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, > + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, > + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, > + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, > + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, > + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, > + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, > + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, > + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, > + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; > +}; > + > +&lpasscc { > + status = "disabled"; > +}; > + > +&lpass_audiocc { > + qcom,adsp-skip-pll; > + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, > + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, > + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, > + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, > + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, > + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, > + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; > + /delete-property/ power-domains; > +}; > + > +&lpass_aon { > + status = "disabled"; > +}; > + > +&lpass_core { > + status = "disabled"; > +}; > + > +&lpass_hm { > + status = "disabled"; > +}; > + > + > &qupv3_id_0 { > status = "okay"; > }; > -- > 2.17.1 > >
On Thu, Feb 08, 2024 at 11:58:36AM +0530, Taniya Das wrote: > Certain clocks are not accessible on QCM6490-IDP and QCS6490-RB3GEN2 boards > thus require them to be marked protected. > > Also disable the LPASS nodes which are not to be used. > Please find a smaller patch, to make the board boot again here: https://lore.kernel.org/linux-arm-msm/20240209-qcm6490-gcc-protected-clocks-v1-1-bd3487b2e7b1@quicinc.com/T/#u > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 54 +++++++++++++++++++- > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 50 +++++++++++++++++- > 2 files changed, 102 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > index 03e97e27d16d..425e4b87490b 100644 > --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: BSD-3-Clause > /* > - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. > */ > > /dts-v1/; > @@ -415,6 +415,58 @@ > }; > }; > > +&gcc { > + protected-clocks = <GCC_AGGRE_NOC_PCIE_1_AXI_CLK> ,<GCC_PCIE_1_AUX_CLK>, > + <GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>, > + <GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, > + <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>, > + <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>, protected-clocks should mark the clocks that Linux must not access. With that in mind, how is listing GCC_PCIE_1_* here compatible with Krishna's patch [1], which clearly shows that Linux is expected to use pcie1. [1] https://lore.kernel.org/linux-arm-msm/20240207-enable_pcie-v1-1-b684afa6371c@quicinc.com/ Regards, Bjorn > + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, > + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, > + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, > + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, > + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, > + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, > + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, > + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, > + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, > + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, > + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, > + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; > +}; > + > +&lpasscc { > + status = "disabled"; > +}; > + > +&lpass_audiocc { > + qcom,adsp-skip-pll; > + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, > + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, > + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, > + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, > + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, > + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, > + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; > + /delete-property/ power-domains; > +}; > + > +&lpass_aon { > + status = "disabled"; > +}; > + > +&lpass_core { > + status = "disabled"; > +}; > + > +&lpass_hm { > + status = "disabled"; > +}; > + > &qupv3_id_0 { > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > index 8bb7d13d85f6..1398b84634c3 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: BSD-3-Clause > /* > - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. > */ > > /dts-v1/; > @@ -413,6 +413,54 @@ > }; > }; > > +&gcc { > + protected-clocks = <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, > + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, > + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, > + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, > + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, > + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, > + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, > + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, > + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, > + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, > + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, > + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; > +}; > + > +&lpasscc { > + status = "disabled"; > +}; > + > +&lpass_audiocc { > + qcom,adsp-skip-pll; > + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, > + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, > + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, > + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, > + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, > + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, > + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; > + /delete-property/ power-domains; > +}; > + > +&lpass_aon { > + status = "disabled"; > +}; > + > +&lpass_core { > + status = "disabled"; > +}; > + > +&lpass_hm { > + status = "disabled"; > +}; > + > + > &qupv3_id_0 { > status = "okay"; > }; > -- > 2.17.1 >
On 8.02.2024 07:28, Taniya Das wrote: > Certain clocks are not accessible on QCM6490-IDP and QCS6490-RB3GEN2 boards > thus require them to be marked protected. > > Also disable the LPASS nodes which are not to be used. > > Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > --- One patch per board, please > arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 54 +++++++++++++++++++- > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 50 +++++++++++++++++- > 2 files changed, 102 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > index 03e97e27d16d..425e4b87490b 100644 > --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > @@ -1,6 +1,6 @@ > // SPDX-License-Identifier: BSD-3-Clause > /* > - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. > */ > > /dts-v1/; > @@ -415,6 +415,58 @@ > }; > }; > > +&gcc { > + protected-clocks = <GCC_AGGRE_NOC_PCIE_1_AXI_CLK> ,<GCC_PCIE_1_AUX_CLK>, > + <GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>, > + <GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, > + <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>, > + <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>, > + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, > + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, > + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, > + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, > + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, > + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, > + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, > + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, > + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, > + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, > + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, > + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; Why on earth are clocks such as USB sleep reserved? How does it work? > +}; > + > +&lpasscc { > + status = "disabled"; > +}; > + > +&lpass_audiocc { > + qcom,adsp-skip-pll; > + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, > + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, > + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, > + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, > + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, > + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, > + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, > + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; > + /delete-property/ power-domains; > +}; This literally disables all clocks that come out of this controller, why not just set status = "reserved"? > + > +&lpass_aon { > + status = "disabled"; > +}; > + > +&lpass_core { > + status = "disabled"; > +}; > + > +&lpass_hm { > + status = "disabled"; > +}; These three are status = "reserved" by default already, so it's a NOP.. Konrad
Thanks for the review. On 2/9/2024 10:16 PM, Konrad Dybcio wrote: > On 8.02.2024 07:28, Taniya Das wrote: >> Certain clocks are not accessible on QCM6490-IDP and QCS6490-RB3GEN2 boards >> thus require them to be marked protected. >> >> Also disable the LPASS nodes which are not to be used. >> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> --- > > One patch per board, please Sure, I will update the same in the next patch series. > >> arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 54 +++++++++++++++++++- >> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 50 +++++++++++++++++- >> 2 files changed, 102 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> index 03e97e27d16d..425e4b87490b 100644 >> --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> @@ -1,6 +1,6 @@ >> // SPDX-License-Identifier: BSD-3-Clause >> /* >> - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. >> + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> /dts-v1/; >> @@ -415,6 +415,58 @@ >> }; >> }; >> >> +&gcc { >> + protected-clocks = <GCC_AGGRE_NOC_PCIE_1_AXI_CLK> ,<GCC_PCIE_1_AUX_CLK>, >> + <GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>, >> + <GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, >> + <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>, >> + <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>, >> + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, >> + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, >> + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, >> + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, >> + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, >> + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, >> + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, >> + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, >> + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, >> + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, >> + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, >> + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, >> + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; > > Why on earth are clocks such as USB sleep reserved? How does it work? On IDP platform these clocks are to be kept protected and no exposure of the USB30/PCIE clocks. That was the reason to keep them in the list. > >> +}; >> + >> +&lpasscc { >> + status = "disabled"; >> +}; >> + >> +&lpass_audiocc { >> + qcom,adsp-skip-pll; >> + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, >> + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, >> + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, >> + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, >> + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, >> + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, >> + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; >> + /delete-property/ power-domains; >> +}; > > This literally disables all clocks that come out of this controller, why > not just set status = "reserved"? > We need the resets from the clock controller to be exposed for the audio SW driver to be able to perform resets and the rest of the clocks would be controlled from the Low Power Audio Firmware. >> + >> +&lpass_aon { >> + status = "disabled"; >> +}; >> + >> +&lpass_core { >> + status = "disabled"; >> +}; >> + >> +&lpass_hm { >> + status = "disabled"; >> +}; > > These three are status = "reserved" by default already, so it's a NOP.. > Yes, I see the patch to keep them reserved, I will remove them in the next series. > Konrad
Thanks Bjorn for your review. On 2/9/2024 10:07 PM, Bjorn Andersson wrote: > On Thu, Feb 08, 2024 at 11:58:36AM +0530, Taniya Das wrote: >> Certain clocks are not accessible on QCM6490-IDP and QCS6490-RB3GEN2 boards >> thus require them to be marked protected. >> >> Also disable the LPASS nodes which are not to be used. >> > > Please find a smaller patch, to make the board boot again here: > > https://lore.kernel.org/linux-arm-msm/20240209-qcm6490-gcc-protected-clocks-v1-1-bd3487b2e7b1@quicinc.com/T/#u > >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 54 +++++++++++++++++++- >> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 50 +++++++++++++++++- >> 2 files changed, 102 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> index 03e97e27d16d..425e4b87490b 100644 >> --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> @@ -1,6 +1,6 @@ >> // SPDX-License-Identifier: BSD-3-Clause >> /* >> - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. >> + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> /dts-v1/; >> @@ -415,6 +415,58 @@ >> }; >> }; >> >> +&gcc { >> + protected-clocks = <GCC_AGGRE_NOC_PCIE_1_AXI_CLK> ,<GCC_PCIE_1_AUX_CLK>, >> + <GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>, >> + <GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, >> + <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>, >> + <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>, > > protected-clocks should mark the clocks that Linux must not access. > > With that in mind, how is listing GCC_PCIE_1_* here compatible with > Krishna's patch [1], which clearly shows that Linux is expected to use > pcie1. > > [1] https://lore.kernel.org/linux-arm-msm/20240207-enable_pcie-v1-1-b684afa6371c@quicinc.com/ > > Regards, > Bjorn I checked the patch and it is only expected to be used on RB3 boards and not on IDP platforms. > >> + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, >> + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, >> + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, >> + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, >> + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, >> + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, >> + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, >> + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, >> + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, >> + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, >> + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, >> + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, >> + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; >> +}; >> + >> +&lpasscc { >> + status = "disabled"; >> +}; >> + >> +&lpass_audiocc { >> + qcom,adsp-skip-pll; >> + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, >> + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, >> + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, >> + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, >> + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, >> + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, >> + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; >> + /delete-property/ power-domains; >> +}; >> + >> +&lpass_aon { >> + status = "disabled"; >> +}; >> + >> +&lpass_core { >> + status = "disabled"; >> +}; >> + >> +&lpass_hm { >> + status = "disabled"; >> +}; >> + >> &qupv3_id_0 { >> status = "okay"; >> }; >> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> index 8bb7d13d85f6..1398b84634c3 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> @@ -1,6 +1,6 @@ >> // SPDX-License-Identifier: BSD-3-Clause >> /* >> - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. >> + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> /dts-v1/; >> @@ -413,6 +413,54 @@ >> }; >> }; >> >> +&gcc { >> + protected-clocks = <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, >> + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, >> + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, >> + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, >> + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, >> + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, >> + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, >> + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, >> + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, >> + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, >> + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, >> + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, >> + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; >> +}; >> + >> +&lpasscc { >> + status = "disabled"; >> +}; >> + >> +&lpass_audiocc { >> + qcom,adsp-skip-pll; >> + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, >> + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, >> + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, >> + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, >> + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, >> + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, >> + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; >> + /delete-property/ power-domains; >> +}; >> + >> +&lpass_aon { >> + status = "disabled"; >> +}; >> + >> +&lpass_core { >> + status = "disabled"; >> +}; >> + >> +&lpass_hm { >> + status = "disabled"; >> +}; >> + >> + >> &qupv3_id_0 { >> status = "okay"; >> }; >> -- >> 2.17.1 >>
Thanks for your review Dmitry. On 2/8/2024 12:44 PM, Dmitry Baryshkov wrote: > On Thu, 8 Feb 2024 at 08:29, Taniya Das <quic_tdas@quicinc.com> wrote: >> >> Certain clocks are not accessible on QCM6490-IDP and QCS6490-RB3GEN2 boards >> thus require them to be marked protected. >> >> Also disable the LPASS nodes which are not to be used. >> >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 54 +++++++++++++++++++- >> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 50 +++++++++++++++++- >> 2 files changed, 102 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> index 03e97e27d16d..425e4b87490b 100644 >> --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts >> @@ -1,6 +1,6 @@ >> // SPDX-License-Identifier: BSD-3-Clause >> /* >> - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. >> + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> /dts-v1/; >> @@ -415,6 +415,58 @@ >> }; >> }; >> >> +&gcc { >> + protected-clocks = <GCC_AGGRE_NOC_PCIE_1_AXI_CLK> ,<GCC_PCIE_1_AUX_CLK>, >> + <GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>, >> + <GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, >> + <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>, >> + <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>, >> + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, >> + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, >> + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, >> + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, >> + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, >> + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, >> + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, >> + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, >> + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, >> + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, >> + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, >> + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, >> + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; > > This looks like a huge variety of clocks. Are they really not > accessible or are you trying to make Linux stay away from all those > clocks to keep bootloader settings? > These clocks are protected and accessing them from Linux will cause Bus error (NoC) and thus this list grows sometimes. >> +}; >> + >> +&lpasscc { >> + status = "disabled"; >> +}; >> + >> +&lpass_audiocc { >> + qcom,adsp-skip-pll; >> + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, >> + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, >> + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, >> + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, >> + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, >> + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, >> + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; > > This almost looks like a separate compatible. We need to use the reset from this controller, rest all will be controlled via the Low Power Audio Firmware. > >> + /delete-property/ power-domains; >> +}; >> + >> +&lpass_aon { >> + status = "disabled"; > > Should this be "reserved", controlled by ADSP? See how this was > implemented in sc7180.dtsi / sc7180-trogdor.dtsi. > Please consider inverting the logic. Generic ADSP implementation > should be present in sc7280.dtsi and then the non-default ChromeOS > implementation should be a part of sc7280-chrome-common.dtsi. > This I will take care in the next series. >> +}; >> + >> +&lpass_core { >> + status = "disabled"; >> +}; >> + >> +&lpass_hm { >> + status = "disabled"; >> +}; >> + >> &qupv3_id_0 { >> status = "okay"; >> }; >> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> index 8bb7d13d85f6..1398b84634c3 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts >> @@ -1,6 +1,6 @@ >> // SPDX-License-Identifier: BSD-3-Clause >> /* >> - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. >> + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> /dts-v1/; >> @@ -413,6 +413,54 @@ >> }; >> }; >> >> +&gcc { >> + protected-clocks = <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, >> + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, >> + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, >> + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, >> + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, >> + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, >> + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, >> + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, >> + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, >> + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, >> + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, >> + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, >> + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; >> +}; >> + >> +&lpasscc { >> + status = "disabled"; >> +}; >> + >> +&lpass_audiocc { >> + qcom,adsp-skip-pll; >> + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, >> + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, >> + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, >> + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, >> + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, >> + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, >> + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, >> + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; >> + /delete-property/ power-domains; >> +}; >> + >> +&lpass_aon { >> + status = "disabled"; >> +}; >> + >> +&lpass_core { >> + status = "disabled"; >> +}; >> + >> +&lpass_hm { >> + status = "disabled"; >> +}; >> + >> + >> &qupv3_id_0 { >> status = "okay"; >> }; >> -- >> 2.17.1 >> >> > >
On Wed, 6 Mar 2024 at 08:54, Taniya Das <quic_tdas@quicinc.com> wrote: > > Thanks for your review Dmitry. > > On 2/8/2024 12:44 PM, Dmitry Baryshkov wrote: > > On Thu, 8 Feb 2024 at 08:29, Taniya Das <quic_tdas@quicinc.com> wrote: > >> > >> Certain clocks are not accessible on QCM6490-IDP and QCS6490-RB3GEN2 boards > >> thus require them to be marked protected. > >> > >> Also disable the LPASS nodes which are not to be used. > >> > >> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> > >> --- > >> arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 54 +++++++++++++++++++- > >> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 50 +++++++++++++++++- > >> 2 files changed, 102 insertions(+), 2 deletions(-) > >> > >> diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > >> index 03e97e27d16d..425e4b87490b 100644 > >> --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > >> +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts > >> @@ -1,6 +1,6 @@ > >> // SPDX-License-Identifier: BSD-3-Clause > >> /* > >> - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > >> + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. > >> */ > >> > >> /dts-v1/; > >> @@ -415,6 +415,58 @@ > >> }; > >> }; > >> > >> +&gcc { > >> + protected-clocks = <GCC_AGGRE_NOC_PCIE_1_AXI_CLK> ,<GCC_PCIE_1_AUX_CLK>, > >> + <GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>, > >> + <GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, > >> + <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>, > >> + <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>, > >> + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, > >> + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, > >> + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, > >> + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, > >> + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, > >> + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, > >> + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, > >> + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, > >> + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, > >> + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, > >> + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, > >> + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, > >> + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; > > > > This looks like a huge variety of clocks. Are they really not > > accessible or are you trying to make Linux stay away from all those > > clocks to keep bootloader settings? > > > > These clocks are protected and accessing them from Linux will cause Bus > error (NoC) and thus this list grows sometimes. > > >> +}; > >> + > >> +&lpasscc { > >> + status = "disabled"; > >> +}; > >> + > >> +&lpass_audiocc { > >> + qcom,adsp-skip-pll; > >> + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, > >> + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, > >> + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, > >> + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, > >> + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, > >> + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, > >> + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, > >> + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, > >> + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, > >> + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; > > > > This almost looks like a separate compatible. > > We need to use the reset from this controller, rest all will be > controlled via the Low Power Audio Firmware. Not "separate device", but "separate compatible". > > > > >> + /delete-property/ power-domains; > >> +}; > >> + > >> +&lpass_aon { > >> + status = "disabled"; > > > > Should this be "reserved", controlled by ADSP? See how this was > > implemented in sc7180.dtsi / sc7180-trogdor.dtsi. > > Please consider inverting the logic. Generic ADSP implementation > > should be present in sc7280.dtsi and then the non-default ChromeOS > > implementation should be a part of sc7280-chrome-common.dtsi. > > > > This I will take care in the next series. > > >> +}; > >> + > >> +&lpass_core { > >> + status = "disabled"; > >> +}; > >> + > >> +&lpass_hm { > >> + status = "disabled"; > >> +}; > >> + > >> &qupv3_id_0 { > >> status = "okay"; > >> }; > >> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > >> index 8bb7d13d85f6..1398b84634c3 100644 > >> --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > >> +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > >> @@ -1,6 +1,6 @@ > >> // SPDX-License-Identifier: BSD-3-Clause > >> /* > >> - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. > >> + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. > >> */ > >> > >> /dts-v1/; > >> @@ -413,6 +413,54 @@ > >> }; > >> }; > >> > >> +&gcc { > >> + protected-clocks = <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, > >> + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, > >> + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, > >> + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, > >> + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, > >> + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, > >> + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, > >> + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, > >> + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, > >> + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, > >> + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, > >> + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, > >> + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; > >> +}; > >> + > >> +&lpasscc { > >> + status = "disabled"; > >> +}; > >> + > >> +&lpass_audiocc { > >> + qcom,adsp-skip-pll; > >> + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, > >> + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, > >> + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, > >> + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, > >> + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, > >> + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, > >> + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, > >> + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, > >> + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, > >> + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; > >> + /delete-property/ power-domains; > >> +}; > >> + > >> +&lpass_aon { > >> + status = "disabled"; > >> +}; > >> + > >> +&lpass_core { > >> + status = "disabled"; > >> +}; > >> + > >> +&lpass_hm { > >> + status = "disabled"; > >> +}; > >> + > >> + > >> &qupv3_id_0 { > >> status = "okay"; > >> }; > >> -- > >> 2.17.1 > >> > >> > > > > > > -- > Thanks & Regards, > Taniya Das.
diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts index 03e97e27d16d..425e4b87490b 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -415,6 +415,58 @@ }; }; +&gcc { + protected-clocks = <GCC_AGGRE_NOC_PCIE_1_AXI_CLK> ,<GCC_PCIE_1_AUX_CLK>, + <GCC_PCIE_1_AUX_CLK_SRC>, <GCC_PCIE_1_CFG_AHB_CLK>, + <GCC_PCIE_1_MSTR_AXI_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>, + <GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>, + <GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; +}; + +&lpasscc { + status = "disabled"; +}; + +&lpass_audiocc { + qcom,adsp-skip-pll; + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; + /delete-property/ power-domains; +}; + +&lpass_aon { + status = "disabled"; +}; + +&lpass_core { + status = "disabled"; +}; + +&lpass_hm { + status = "disabled"; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 8bb7d13d85f6..1398b84634c3 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: BSD-3-Clause /* - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved. */ /dts-v1/; @@ -413,6 +413,54 @@ }; }; +&gcc { + protected-clocks = <GCC_QSPI_CNOC_PERIPH_AHB_CLK>, <GCC_QSPI_CORE_CLK>, + <GCC_QSPI_CORE_CLK_SRC>,<GCC_USB30_SEC_MASTER_CLK>, + <GCC_USB30_SEC_MASTER_CLK_SRC>, <GCC_USB30_SEC_MOCK_UTMI_CLK>, + <GCC_USB30_SEC_MOCK_UTMI_CLK_SRC>, + <GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC>, <GCC_USB30_SEC_SLEEP_CLK>, + <GCC_USB3_SEC_PHY_AUX_CLK>, <GCC_USB3_SEC_PHY_AUX_CLK_SRC>, + <GCC_USB3_SEC_PHY_COM_AUX_CLK>, <GCC_USB3_SEC_PHY_PIPE_CLK>, + <GCC_USB3_SEC_PHY_PIPE_CLK_SRC>, <GCC_CFG_NOC_LPASS_CLK>, + <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>, <GCC_MSS_CFG_AHB_CLK>, + <GCC_MSS_OFFLINE_AXI_CLK>, <GCC_MSS_SNOC_AXI_CLK>, + <GCC_MSS_Q6_MEMNOC_AXI_CLK>, <GCC_MSS_Q6SS_BOOT_CLK_SRC>, + <GCC_SEC_CTRL_CLK_SRC>, <GCC_WPSS_AHB_CLK>, + <GCC_WPSS_AHB_BDG_MST_CLK>, <GCC_WPSS_RSCP_CLK>; +}; + +&lpasscc { + status = "disabled"; +}; + +&lpass_audiocc { + qcom,adsp-skip-pll; + protected-clocks = <LPASS_AUDIO_CC_CDIV_RX_MCLK_DIV_CLK_SRC>, + <LPASS_AUDIO_CC_CODEC_MEM0_CLK>, <LPASS_AUDIO_CC_CODEC_MEM1_CLK>, + <LPASS_AUDIO_CC_CODEC_MEM2_CLK>, <LPASS_AUDIO_CC_CODEC_MEM_CLK>, + <LPASS_AUDIO_CC_EXT_MCLK0_CLK>, <LPASS_AUDIO_CC_EXT_MCLK0_CLK_SRC>, + <LPASS_AUDIO_CC_EXT_MCLK1_CLK>, <LPASS_AUDIO_CC_EXT_MCLK1_CLK_SRC>, + <LPASS_AUDIO_CC_PLL>, <LPASS_AUDIO_CC_PLL_OUT_AUX2>, + <LPASS_AUDIO_CC_PLL_OUT_AUX2_DIV_CLK_SRC>, + <LPASS_AUDIO_CC_PLL_OUT_MAIN_DIV_CLK_SRC>, + <LPASS_AUDIO_CC_RX_MCLK_2X_CLK>, <LPASS_AUDIO_CC_RX_MCLK_CLK>, + <LPASS_AUDIO_CC_RX_MCLK_CLK_SRC>; + /delete-property/ power-domains; +}; + +&lpass_aon { + status = "disabled"; +}; + +&lpass_core { + status = "disabled"; +}; + +&lpass_hm { + status = "disabled"; +}; + + &qupv3_id_0 { status = "okay"; };
Certain clocks are not accessible on QCM6490-IDP and QCS6490-RB3GEN2 boards thus require them to be marked protected. Also disable the LPASS nodes which are not to be used. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 54 +++++++++++++++++++- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 50 +++++++++++++++++- 2 files changed, 102 insertions(+), 2 deletions(-) -- 2.17.1