From patchwork Fri Feb 16 23:01:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paloma Arellano X-Patchwork-Id: 13560836 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FD981CF81 for ; Fri, 16 Feb 2024 23:02:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708124571; cv=none; b=riPxQd16FdxIat4cRM+PatqW5ZlWBk6jYuOvWPAYWpW+eZ3Q240ptjfwJg5fei2zKfYmg/R4sUkLAYHwSscglONjvy4ttaeKcwr+zgLKeAmk1C0w7n5E/5x55lANKANnyC0HQ4IyNhtEFVovUTtKIpJ7NB8rgD4xEaFFdJhLT1A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708124571; c=relaxed/simple; bh=lIXBY/f6NH/RdBfPGO4hGIta/5Q8a/6XP80QIWX1kG0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qN30t3PYaKmHkvOZJW6lU5AWRN8DH3Zt8RCKndK8IYlCNxGl7OPAmabsemNanXYVz8aeQXiHoRGk7ptowQEoWs/iFM1n3J8SNL+1bQKreLpecdyaVptb1k4xzxLUGvhBTXJZyyJii5r8nubgMA8VxiILXCQWtTaGBpiOPngm47M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=ZzD/9R44; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ZzD/9R44" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41GMtds4007347; Fri, 16 Feb 2024 23:02:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=s7GKlOVkfJsJdGPJFzGXijumOoNZH8brsun2KM72eVI=; b=Zz D/9R44ZRP5ydArSont5yddvg2WqyHQbxIaUkgdOeaZG8oZzjvJFzVo7bj8tMITun gC7jEVwgeZ1gOj059vfzgvKWEZ+STSFMvxAxBdnAnVTRbJ/l5VAFPHTnUc0Tx+VI RYtUe08nq/j1kMtLb26tgjDzNR0wjB+QVtyLk593Y5jIvJmoxSRuKLymDYmUWD59 ErBAjQKxU8OBrBvHkTme90C4XIwoDukeJqq+GCBgUntkHYZqYPCTlhxClykoYofe 2nR9PI6Wi7VMrnNLB1JqVsps/trsF0iHafVO5bEkX59WqriQcqh02ae3JBjADWUQ 6q/4eIOntOaqr5bLAo5Q== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3wa6nk9ax7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Feb 2024 23:02:42 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 41GN2fHY003809 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Feb 2024 23:02:41 GMT Received: from hu-parellan-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 16 Feb 2024 15:02:41 -0800 From: Paloma Arellano To: CC: Paloma Arellano , , , , , , , , , , , Subject: [PATCH v4 01/19] drm/msm/dpu: allow certain formats for CDM for DP Date: Fri, 16 Feb 2024 15:01:49 -0800 Message-ID: <20240216230228.26713-2-quic_parellan@quicinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240216230228.26713-1-quic_parellan@quicinc.com> References: <20240216230228.26713-1-quic_parellan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: uQiuGgnJ0CdYTn4uvW5tGqLAoO3Ca1oo X-Proofpoint-ORIG-GUID: uQiuGgnJ0CdYTn4uvW5tGqLAoO3Ca1oo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-16_22,2024-02-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 phishscore=0 mlxlogscore=589 priorityscore=1501 lowpriorityscore=0 spamscore=0 bulkscore=0 mlxscore=0 adultscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402160182 CDM block supports formats other than H1V2 for DP. Since we are now adding support for CDM over DP, relax the checks to allow all other formats for DP other than H1V2. Changes in v2: - Add fixes tag - Move patch to top of series Fixes: 0afac0ba6024 ("drm/msm/dpu: add dpu_hw_cdm abstraction for CDM block") Signed-off-by: Paloma Arellano Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c index e9cdc7934a499..9016b3ade6bc3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c @@ -186,7 +186,7 @@ static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm) dpu_hw_cdm_setup_cdwn(ctx, cdm); if (cdm->output_type == CDM_CDWN_OUTPUT_HDMI) { - if (fmt->chroma_sample != DPU_CHROMA_H1V2) + if (fmt->chroma_sample == DPU_CHROMA_H1V2) return -EINVAL; /*unsupported format */ opmode = CDM_HDMI_PACK_OP_MODE_EN; opmode |= (fmt->chroma_sample << 1);