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Tue, 20 Feb 2024 19:42:53 -0800 (PST) Received: from [127.0.1.1] ([117.207.28.224]) by smtp.gmail.com with ESMTPSA id o23-20020a056a001b5700b006e466369645sm4436231pfv.132.2024.02.20.19.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 19:42:53 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 21 Feb 2024 09:11:59 +0530 Subject: [PATCH 13/21] arm64: dts: qcom: sc8180x: Add PCIe bridge node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240221-pcie-qcom-bridge-dts-v1-13-6c6df0f9450d@linaro.org> References: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org> In-Reply-To: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1867; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=ntCfHbJqyHo2IKloDJny626bPqnVLcdHkMXuobbQPMI=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl1XEIB2OO7XO/U6sELwLIt1TGK59monBn7moxn 6dyHg9lzGyJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZdVxCAAKCRBVnxHm/pHO 9XX7B/94Zww9TR1j1Q15e64KFzc/uZLpFwM34IIZB95PjFpVYogq2AQWzgy3naGxRLAyHkl0d7W 2Bu9uCBLquvDI9nK5DyjS0qvy9Cx7UExTMBgUGfJt1Ix8hzpEc8gAING+JMwnBwjxPEv+msS3X/ MIyCYPEx9xaJjombvLjqkCkYsqDnwsLNoCWb+rjNNJqaAOb5IIasDG3KVBReN8dqLFOu8sYcPXF GSCgIfXGB97dnz2qIxXyF0SQLunP6hKSZZ6qRZBtmW5xwma4NFG3+j9JXowBJJgBnYAhbCBbeLc i19l8ti+zudL1i7KbRHEjzmXiTar/3jnKbUCAKAJqSOEgyJi X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 40 +++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 0430d99091e3..a6134f454e53 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1754,6 +1754,16 @@ pcie0: pcie@1c00000 { dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1851,6 +1861,16 @@ pcie3: pcie@1c08000 { dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3_phy: phy@1c0c000 { @@ -1949,6 +1969,16 @@ pcie1: pcie@1c10000 { dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c16000 { @@ -2047,6 +2077,16 @@ pcie2: pcie@1c18000 { dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2_phy: phy@1c1c000 {