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Tue, 20 Feb 2024 19:42:25 -0800 (PST) Received: from [127.0.1.1] ([117.207.28.224]) by smtp.gmail.com with ESMTPSA id o23-20020a056a001b5700b006e466369645sm4436231pfv.132.2024.02.20.19.42.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 19:42:25 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 21 Feb 2024 09:11:51 +0530 Subject: [PATCH 05/21] arm64: dts: qcom: sm8450: Add PCIe bridge node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240221-pcie-qcom-bridge-dts-v1-5-6c6df0f9450d@linaro.org> References: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org> In-Reply-To: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=1249; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=wMGBDo8PfZNtRjeSzpd4083aE4V7NiguAVNg298g23E=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl1XEGPFkJEG2R9ixKQaN7nKfcNZLT7FLZdrDd6 HuoPkAS7DGJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZdVxBgAKCRBVnxHm/pHO 9Z17B/43E3+z6dq5RkjNMdjw/9k5gftRx7SBxgj9e3HiDqAqDtW3QFTVjYv5Qdi5U3HL083zD5C xJkOLw32bWrVdwiQB67tqljUNfGTUZUAyRN6D4YL4iyZKr3WSegnmwwZF82nCYoSEcey5AYoZO0 nRrhDxm+SvJOe77ZGesTk1RaGyL/87gBjhKSDC5ZGSCE1GX3Sp+ZrWiPD6j9dmnVwLcdi4Hm+91 Yeb6EtmgeaHTcCFDazT0jutoNHNVDpi3xmcfEaYDsdkbnq7OdMg34BIN7/slsjIklULkgcI4vw4 bUAjCSKrXPD3uDAfyY6OzDU3McXZGWA//4OhdosQO/1PKF61 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 01e4dfc4babd..e874cc4f8e6f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1824,6 +1824,16 @@ pcie0: pcie@1c00000 { pinctrl-0 = <&pcie0_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -1931,6 +1941,16 @@ pcie1: pcie@1c08000 { pinctrl-0 = <&pcie1_default_state>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 {