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Tue, 20 Feb 2024 19:42:39 -0800 (PST) Received: from [127.0.1.1] ([117.207.28.224]) by smtp.gmail.com with ESMTPSA id o23-20020a056a001b5700b006e466369645sm4436231pfv.132.2024.02.20.19.42.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 19:42:38 -0800 (PST) From: Manivannan Sadhasivam Date: Wed, 21 Feb 2024 09:11:55 +0530 Subject: [PATCH 09/21] arm64: dts: qcom: sc8280xp: Add PCIe bridge node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240221-pcie-qcom-bridge-dts-v1-9-6c6df0f9450d@linaro.org> References: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org> In-Reply-To: <20240221-pcie-qcom-bridge-dts-v1-0-6c6df0f9450d@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=2700; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=XwgmeGggFrXeetR+EYAdr6Z2A4DtJUzK6YNLFgLFJC4=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl1XEHVShYIbB8TBTLfW8as/DVemrTl39xLMnVH PHUKnCg/kuJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZdVxBwAKCRBVnxHm/pHO 9dEMB/sHUSKJDzXFGuECJ6iPlaykTCqH3OINz0eYVlbxMG9/x1kZ3U7G0WClA4vHDRq5regAbNG IXj82rqC2LAmxtaj0VWn71/r3QArbOP0HeVV+aJkhZJ/vFf135QH/0IBNg0oh6EBU/+75iTfNdK zAC6tCvnC6uz8JrImXvkinJu8ARwZkmu5Z9S3ONElk8IEzPS0HIwjjQ0fzz6AH1ZM7I/WUfcbih Z8IJ0V74+ZCAdtaC5BnYrrye+W0yzCF40hYQ+e9j1KxV4A3YSlLgscwSFES301Adnju6qtpiRzx nXrAU8pr4i7xa2BO7WX5Hag9krNRGDtsTrleiHq0IIpcFpbG X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. While at it, let's remove the bridge properties from board dts as they are now redundant. Signed-off-by: Manivannan Sadhasivam --- .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 8 ----- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 40 ++++++++++++++++++++++ 2 files changed, 40 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index def3976bd5bb..f0a0115e08fa 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -733,14 +733,6 @@ &pcie4 { status = "okay"; pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - ranges; - - bus-range = <0x01 0xff>; - wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index febf28356ff8..37d9e01d7e4e 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1779,6 +1779,16 @@ pcie4: pcie@1c00000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie4_phy: phy@1c06000 { @@ -1877,6 +1887,16 @@ pcie3b: pcie@1c08000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3b_phy: phy@1c0e000 { @@ -1975,6 +1995,16 @@ pcie3a: pcie@1c10000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3a_phy: phy@1c14000 { @@ -2076,6 +2106,16 @@ pcie2b: pcie@1c18000 { phy-names = "pciephy"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2b_phy: phy@1c1e000 {