Message ID | 20240321-pcie-qcom-bridge-dts-v2-16-1eb790c53e43@linaro.org (mailing list archive) |
---|---|
State | Accepted |
Commit | 52358c64937e982d3cdcf64be58f08f30d8e518c |
Headers | show
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Series |
Add PCIe bridge node in DT for Qcom SoCs
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diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 4e29adea570a..17ab6c475958 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -907,6 +907,16 @@ pcie0: pcie@20000000 { "axi_s_sticky"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; };
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)