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Thu, 21 Mar 2024 04:17:45 -0700 (PDT) Received: from [127.0.1.1] ([2409:40f4:102b:a64b:d832:a82a:837c:6d3]) by smtp.gmail.com with ESMTPSA id ka6-20020a056a00938600b006e7324d32bbsm5531120pfb.122.2024.03.21.04.17.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Mar 2024 04:17:45 -0700 (PDT) From: Manivannan Sadhasivam Date: Thu, 21 Mar 2024 16:46:36 +0530 Subject: [PATCH v2 16/21] arm64: dts: qcom: ipq6018: Add PCIe bridge node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240321-pcie-qcom-bridge-dts-v2-16-1eb790c53e43@linaro.org> References: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> In-Reply-To: <20240321-pcie-qcom-bridge-dts-v2-0-1eb790c53e43@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org, Rob Herring Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=openpgp-sha256; l=864; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=tlr2lasCyCa/zgi8oI+AluN7Tqvxvjw2NcUxkA1441s=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl/BcNhJc1Bn8KeL49KiM2lfnVfLHkQjH4OTaM3 qMaeoeCuMGJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZfwXDQAKCRBVnxHm/pHO 9a+4B/0cTPSBfqxceWlGyh67ruYuBrsLJPCj+ulDGCwQsWbAIQp+2OkA60/eCIy7fcaQT0QXwwV t7jXRsYHvJsac/43YiWJI2+egjtjSv/L1RES+ccosM37FMbSz09Wv+F06ak+d0K/5c+Ybt5/dge 2VvmDudjcJQhcllmEL5orREejaUuafroOyrk9ZYhbllgtX2duoA2cTH5iNpZFbWbogDfNLkmmnm B8UEKDeozQRMoPLbg9pPVjUdHfhe9SJL5d+OSwjJklPX/BlhR//H+3Odc85X/cbWWb7j5rdQ1IG L6CbZDfEGhSrSODEGNepktsTGATGcD27hxKzliMRDAaXACWQ X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 4e29adea570a..17ab6c475958 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -907,6 +907,16 @@ pcie0: pcie@20000000 { "axi_s_sticky"; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; };