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Thu, 21 Mar 2024 09:26:06 GMT Received: from hu-jkona-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 21 Mar 2024 02:26:00 -0700 From: Jagadeesh Kona To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: Vladimir Zapolskiy , , , , , Taniya Das , Jagadeesh Kona , "Satya Priya Kakitapalli" , Ajit Pandey , Imran Shaik , "Krzysztof Kozlowski" Subject: [PATCH V2 RESEND 1/6] dt-bindings: clock: qcom: Add SM8650 video clock controller Date: Thu, 21 Mar 2024 14:55:24 +0530 Message-ID: <20240321092529.13362-2-quic_jkona@quicinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240321092529.13362-1-quic_jkona@quicinc.com> References: <20240321092529.13362-1-quic_jkona@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _C2uz-RvRJ93jrZ0wNardMJrQz-ZHQd_ X-Proofpoint-ORIG-GUID: _C2uz-RvRJ93jrZ0wNardMJrQz-ZHQd_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 mlxlogscore=999 lowpriorityscore=0 clxscore=1015 priorityscore=1501 phishscore=0 impostorscore=0 spamscore=0 suspectscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403140001 definitions=main-2403210064 Extend device tree bindings of SM8450 videocc to add support for SM8650 videocc. While it at, fix the incorrect header include in sm8450 videocc yaml documentation. Signed-off-by: Jagadeesh Kona Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 4 +++- include/dt-bindings/clock/qcom,sm8450-videocc.h | 8 +++++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index bad8f019a8d3..79f55620eb70 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -8,18 +8,20 @@ title: Qualcomm Video Clock & Reset Controller on SM8450 maintainers: - Taniya Das + - Jagadeesh Kona description: | Qualcomm video clock control module provides the clocks, resets and power domains on SM8450. - See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h + See also:: include/dt-bindings/clock/qcom,sm8450-videocc.h properties: compatible: enum: - qcom,sm8450-videocc - qcom,sm8550-videocc + - qcom,sm8650-videocc reg: maxItems: 1 diff --git a/include/dt-bindings/clock/qcom,sm8450-videocc.h b/include/dt-bindings/clock/qcom,sm8450-videocc.h index 9d795adfe4eb..ecfebe52e4bb 100644 --- a/include/dt-bindings/clock/qcom,sm8450-videocc.h +++ b/include/dt-bindings/clock/qcom,sm8450-videocc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8450_H @@ -19,6 +19,11 @@ #define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9 #define VIDEO_CC_PLL0 10 #define VIDEO_CC_PLL1 11 +#define VIDEO_CC_MVS0_SHIFT_CLK 12 +#define VIDEO_CC_MVS0C_SHIFT_CLK 13 +#define VIDEO_CC_MVS1_SHIFT_CLK 14 +#define VIDEO_CC_MVS1C_SHIFT_CLK 15 +#define VIDEO_CC_XO_CLK_SRC 16 /* VIDEO_CC power domains */ #define VIDEO_CC_MVS0C_GDSC 0 @@ -34,5 +39,6 @@ #define CVP_VIDEO_CC_MVS1C_BCR 4 #define VIDEO_CC_MVS0C_CLK_ARES 5 #define VIDEO_CC_MVS1C_CLK_ARES 6 +#define VIDEO_CC_XO_CLK_ARES 7 #endif