diff mbox series

arm64: dts: qcom: sm8650: remove useless enablement of mdss_mdp

Message ID 20240325-topic-sm8x50-upstream-leave-mdss-enabled-by-default-v1-1-f1b380132075@linaro.org (mailing list archive)
State Accepted
Commit 6aeeb9456943ce166211231f72e8723731ad116b
Headers show
Series arm64: dts: qcom: sm8650: remove useless enablement of mdss_mdp | expand

Commit Message

Neil Armstrong March 25, 2024, 8:34 a.m. UTC
The MDP/DPU device is not disabled by default, so there is not point in
enabling it in the board DTS file.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ----
 arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ----
 2 files changed, 8 deletions(-)


---
base-commit: 4cece764965020c22cff7665b18a012006359095
change-id: 20240325-topic-sm8x50-upstream-leave-mdss-enabled-by-default-493739dcd1f3

Best regards,

Comments

Bjorn Andersson April 21, 2024, 10:29 p.m. UTC | #1
On Mon, 25 Mar 2024 09:34:33 +0100, Neil Armstrong wrote:
> The MDP/DPU device is not disabled by default, so there is not point in
> enabling it in the board DTS file.
> 
> 

Applied, thanks!

[1/1] arm64: dts: qcom: sm8650: remove useless enablement of mdss_mdp
      commit: 6aeeb9456943ce166211231f72e8723731ad116b

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
index 4450273f9667..d04ceaa73c2b 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts
@@ -641,10 +641,6 @@  &mdss_dsi0_phy {
 	status = "okay";
 };
 
-&mdss_mdp {
-	status = "okay";
-};
-
 &pcie_1_phy_aux_clk {
 	clock-frequency = <1000>;
 };
diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
index b07cac2e5bc8..e0e4587f08c4 100644
--- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
+++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts
@@ -827,10 +827,6 @@  &mdss_dp0_out {
 	remote-endpoint = <&usb_dp_qmpphy_dp_in>;
 };
 
-&mdss_mdp {
-	status = "okay";
-};
-
 &pcie_1_phy_aux_clk {
 	clock-frequency = <1000>;
 };