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[87.246.222.101]) by smtp.gmail.com with ESMTPSA id y3-20020a05651c020300b002d429304a20sm116880ljn.8.2024.04.05.01.41.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Apr 2024 01:41:37 -0700 (PDT) From: Konrad Dybcio Date: Fri, 05 Apr 2024 10:41:31 +0200 Subject: [PATCH 3/6] drm/msm/adreno: Allow specifying default speedbin value Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240405-topic-smem_speedbin-v1-3-ce2b864251b1@linaro.org> References: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> In-Reply-To: <20240405-topic-smem_speedbin-v1-0-ce2b864251b1@linaro.org> To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.13-dev-0438c From: Neil Armstrong Usually, speedbin 0 is the "super SKU", a.k.a the one which can clock the highest. Falling back to it when things go wrong is largely suboptimal, as more often than not, the top frequencies are not supposed to work on other bins. Let the developer specify the intended "lowest common denominator" bin in struct adreno_info. If not specified, partial struct initialization will ensure it's set to zero, retaining previous behavior. Signed-off-by: Neil Armstrong [Konrad: clean up, add commit message] Signed-off-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0674aca0f8a3..4cbdfabbcee5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2915,7 +2915,7 @@ static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *i DRM_DEV_ERROR(dev, "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", speedbin); - supp_hw = BIT(0); /* Default */ + supp_hw = BIT(info->default_speedbin); /* Default */ } ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 77526892eb8c..460b399be37b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -110,6 +110,7 @@ struct adreno_info { * {SHRT_MAX, 0} sentinal. */ struct adreno_speedbin *speedbins; + unsigned int default_speedbin; }; #define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 }