From patchwork Wed Apr 17 13:28:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sibi Sankar X-Patchwork-Id: 13633366 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12E1C1420D7; Wed, 17 Apr 2024 13:29:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713360577; cv=none; b=dFFc0mbrsU+D83XZk7o172H4J8D5B4+mwE6eiezpZ0ReihdJEjroMlrHrAxbCuj/umxw8yFgOlX10cRMPybMAKT+rnmPuieQBJnXy3637w4LjFS8mByXEf+zIWD9qTrzzzx9pplkhK3SvdfgX2m6mO7L6/oNIix1TYcwbCqrhGg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713360577; c=relaxed/simple; bh=S34LT+KdmU7ODct+ieDUiZbVMcspGvBPi+rdQvBzCs0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OW5LYAoUh+v5f0gabngN5WE8cPs449dZm4i2pHmxk/iz4aSDszQrZGN5JxdksJmHDA1wldXEzPZnVj0jfqIYA5IZwOeX3TkzXG0d6+AMpAts6HCwRL1JpeKxMOfME1xFb7/Kw6WINcdX8q99S5qheX5aKbF+F/xB6Onh/ZyAdas= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=llnImkZz; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="llnImkZz" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 43HAqscn030954; Wed, 17 Apr 2024 13:29:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=a9v+ci73TZqDYy1Naij/JSevMBPrXQR0zb5hSZYtCMI=; b=ll nImkZzLlcPiomdjjTkYaJ5jSynFQ/L4rcMBk63mK4AdxWdnThhNw8/BQjqnsgO2+ gImCvbw4b+ZH4DLfZEhkneay8pjhIKHGymRaM/Q/QDu86LrIkxGwdsRcDfS9d98L 0JblGKej0UKy1lPx99jpDV2DW06qRkN4VEoZ4iJc6HYteK+FTZfMc1YbqX05+qNV H95okdlGTxnxzJToJ5teMiqtWkQqwPm4Y6YuHoG4eycSDBR6wSdfEkirUns0phCx mV7sirF4Alm+JaiGlyKgpeRZ85Q85meCmOO15/8eEadLoCosaSRZGoUryHqi7Wbe Ys8s2gBFJ3/e9jgk79aw== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3xjd0x8c0r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Apr 2024 13:29:29 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 43HDTSjH019805 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Apr 2024 13:29:28 GMT Received: from hu-sibis-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 17 Apr 2024 06:29:22 -0700 From: Sibi Sankar To: , , , , , , , CC: , , , , , , , , , , Rob Herring Subject: [PATCH V3 1/5] dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings Date: Wed, 17 Apr 2024 18:58:52 +0530 Message-ID: <20240417132856.1106250-2-quic_sibis@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240417132856.1106250-1-quic_sibis@quicinc.com> References: <20240417132856.1106250-1-quic_sibis@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: MRJMgo0mLYgblFaYq91GMKtvIGAb8SGl X-Proofpoint-ORIG-GUID: MRJMgo0mLYgblFaYq91GMKtvIGAb8SGl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-04-17_10,2024-04-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 phishscore=0 clxscore=1015 suspectscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2404010003 definitions=main-2404170092 Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox controller. Reviewed-by: Rob Herring Signed-off-by: Sibi Sankar --- v2: * Pickup Rb from Dimitry. .../bindings/mailbox/qcom,cpucp-mbox.yaml | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml new file mode 100644 index 000000000000..491b0a05e630 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller + +maintainers: + - Sibi Sankar + +description: + The CPUSS Control Processor (CPUCP) mailbox controller enables communication + between AP and CPUCP by acting as a doorbell between them. + +properties: + compatible: + items: + - const: qcom,x1e80100-cpucp-mbox + + reg: + items: + - description: CPUCP rx register region + - description: CPUCP tx register region + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + + mailbox@17430000 { + compatible = "qcom,x1e80100-cpucp-mbox"; + reg = <0x17430000 0x10000>, <0x18830000 0x10000>; + interrupts = ; + #mbox-cells = <1>; + };