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Mon, 22 Apr 2024 01:33:15 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id j19-20020a05600c1c1300b004161bffa48csm15978786wms.40.2024.04.22.01.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Apr 2024 01:33:15 -0700 (PDT) From: Neil Armstrong Date: Mon, 22 Apr 2024 10:33:11 +0200 Subject: [PATCH v3 1/3] arm64: dts: qcom: sm8450: remove pcie-1-phy-aux-clk and add pcie1_phy pcie1_phy_aux_clk Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-1-799475a27cce@linaro.org> References: <20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@linaro.org> In-Reply-To: <20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v3-0-799475a27cce@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Dmitry Baryshkov X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Remove the dummy pcie-1-phy-aux-clk clock and replace with the pcie1_phy provided QMP_PCIE_PHY_AUX_CLK. Reviewed-by: Dmitry Baryshkov Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 616461fcbab9..71797f337d19 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -754,8 +754,8 @@ gcc: clock-controller@100000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_phy>, - <&pcie1_phy>, - <0>, + <&pcie1_phy QMP_PCIE_PIPE_CLK>, + <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, @@ -2000,8 +2000,8 @@ pcie1_phy: phy@1c0e000 { "rchng", "pipe"; - clock-output-names = "pcie_1_pipe_clk"; - #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk", "pcie_1_phy_aux_clk"; + #clock-cells = <1>; #phy-cells = <0>;