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(cpc115152-dals23-2-0-cust532.20-2.cable.virginm.net. [86.12.82.21]) by smtp.gmail.com with ESMTPSA id bg11-20020a05600c3c8b00b0041a9c3444a6sm11235579wmb.28.2024.04.25.06.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Apr 2024 06:44:44 -0700 (PDT) From: Connor Abbott To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Cc: Connor Abbott Subject: [PATCH 1/6] arm64: dts: qcom: sm8650: Fix GPU cx_mem size Date: Thu, 25 Apr 2024 14:43:49 +0100 Message-Id: <20240425134354.1233862-2-cwabbott0@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20240425134354.1233862-1-cwabbott0@gmail.com> References: <20240425134354.1233862-1-cwabbott0@gmail.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This is doubled compared to previous GPUs. We can't access the new SW_FUSE_VALUE register without this. Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes") Signed-off-by: Connor Abbott --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 658ad2b41c5a..78b8944eaab2 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2607,7 +2607,7 @@ tcsr: clock-controller@1fc0000 { gpu: gpu@3d00000 { compatible = "qcom,adreno-43051401", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, - <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d9e000 0x0 0x2000>, <0x0 0x03d61000 0x0 0x800>; reg-names = "kgsl_3d0_reg_memory", "cx_mem",