| Message ID | 20240426-a750-raytracing-v2-1-562ac9866d63@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | drm/msm: Support a750 "software fuse" for raytracing | expand |
On Fri, 26 Apr 2024 at 21:34, Connor Abbott <cwabbott0@gmail.com> wrote: > > This is doubled compared to previous GPUs. We can't access the new > SW_FUSE_VALUE register without this. > > Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes") > Signed-off-by: Connor Abbott <cwabbott0@gmail.com> > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 26.04.2024 8:33 PM, Connor Abbott wrote: > This is doubled compared to previous GPUs. We can't access the new > SW_FUSE_VALUE register without this. > > Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes") > Signed-off-by: Connor Abbott <cwabbott0@gmail.com> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad
On 26/04/2024 20:33, Connor Abbott wrote: > This is doubled compared to previous GPUs. We can't access the new > SW_FUSE_VALUE register without this. > > Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes") > Signed-off-by: Connor Abbott <cwabbott0@gmail.com> > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index 658ad2b41c5a..78b8944eaab2 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -2607,7 +2607,7 @@ tcsr: clock-controller@1fc0000 { > gpu: gpu@3d00000 { > compatible = "qcom,adreno-43051401", "qcom,adreno"; > reg = <0x0 0x03d00000 0x0 0x40000>, > - <0x0 0x03d9e000 0x0 0x1000>, > + <0x0 0x03d9e000 0x0 0x2000>, > <0x0 0x03d61000 0x0 0x800>; > reg-names = "kgsl_3d0_reg_memory", > "cx_mem", > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 658ad2b41c5a..78b8944eaab2 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2607,7 +2607,7 @@ tcsr: clock-controller@1fc0000 { gpu: gpu@3d00000 { compatible = "qcom,adreno-43051401", "qcom,adreno"; reg = <0x0 0x03d00000 0x0 0x40000>, - <0x0 0x03d9e000 0x0 0x1000>, + <0x0 0x03d9e000 0x0 0x2000>, <0x0 0x03d61000 0x0 0x800>; reg-names = "kgsl_3d0_reg_memory", "cx_mem",
This is doubled compared to previous GPUs. We can't access the new SW_FUSE_VALUE register without this. Fixes: db33633b05c0 ("arm64: dts: qcom: sm8650: add GPU nodes") Signed-off-by: Connor Abbott <cwabbott0@gmail.com> --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)