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Mon, 27 May 2024 07:23:31 -0700 (PDT) Received: from [127.0.1.1] ([112.64.61.67]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-6f8fbd3eb67sm5109895b3a.19.2024.05.27.07.23.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 07:23:30 -0700 (PDT) From: Jun Nie Date: Mon, 27 May 2024 22:21:47 +0800 Subject: [PATCH v5 1/6] drm/msm/dpu: fix video mode DSC for DSI Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240527-msm-drm-dsc-dsi-video-upstream-4-v5-1-f797ffba4682@linaro.org> References: <20240527-msm-drm-dsc-dsi-video-upstream-4-v5-0-f797ffba4682@linaro.org> In-Reply-To: <20240527-msm-drm-dsc-dsi-video-upstream-4-v5-0-f797ffba4682@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Jessica Zhang , Vinod Koul Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Jonathan Marek X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1716819804; l=3468; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=pcO3EpSEffMXfzg3qm9/56HyKCoO+GZpl6408uIpjZY=; b=1A5BlK6c1bwwAerpYBl8UlV6cF5n3ZbY3fE8Nds6gp7rWU/K/IBq1VVN1PiZ+uWBQGtopy1WL PbEDmwmC249DHdk1GblzbVPzt8mM+9JWPyReTQIY1dC8ARwGDqrxOZy X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= From: Jonathan Marek Add width change in DPU timing for DSC compression case to work with DSI video mode. Signed-off-by: Jonathan Marek Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 ++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 18 ++++++++++++++++++ 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 119f3ea50a7c..48cef6e79c70 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -564,7 +564,7 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) return (num_dsc > 0) && (num_dsc > intf_count); } -static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) +struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) { struct msm_drm_private *priv = drm_enc->dev->dev_private; struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index 002e89cc1705..2167c46c1a45 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -334,6 +334,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( */ unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); +/** + * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder + * This helper function is used by physical encoder to get DSC config + * used for this encoder. + * @drm_enc: Pointer to encoder structure + */ +struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc); + /** * dpu_encoder_get_drm_fmt - return DRM fourcc format * @phys_enc: Pointer to physical encoder structure diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index ef69c2f408c3..925ec6ada0e1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -11,6 +11,7 @@ #include "dpu_trace.h" #include "disp/msm_disp_snapshot.h" +#include #include #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \ @@ -115,6 +116,23 @@ static void drm_mode_to_intf_timing_params( timing->h_front_porch = timing->h_front_porch >> 1; timing->hsync_pulse_width = timing->hsync_pulse_width >> 1; } + + /* + * for DSI, if compression is enabled, then divide the horizonal active + * timing parameters by compression ratio. bits of 3 components(R/G/B) + * is compressed into bits of 1 pixel. + */ + if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) { + struct drm_dsc_config *dsc = + dpu_encoder_get_dsc_config(phys_enc->parent); + /* + * TODO: replace drm_dsc_get_bpp_int with logic to handle + * fractional part if there is fraction + */ + timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / + (dsc->bits_per_component * 3); + timing->xres = timing->width; + } } static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing)