| Message ID | 20240527-x1e80100-dts-pmic-glink-v1-1-7ea5c8eb4d2b@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: qcom: x1e80100: Describe 3 USB Type-C connectors currently used | expand |
On Mon, May 27, 2024 at 11:07:27AM +0300, Abel Vesa wrote: > All PHYs, being QMP combo type, implement both USB and DP. Add the port > nodes for high-speed, super-speed and DP to all 3 PHYs belonging to > USB1. Also add the counterpart nodes for the DWC3 controllers. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 123 +++++++++++++++++++++++++++++++-- > 1 file changed, 117 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 5f90a0b3c016..63e85c5ea6c9 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -2543,6 +2543,29 @@ usb_1_ss0_qmpphy: phy@fd5000 { > #phy-cells = <1>; > > status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + usb_1_ss0_qmpphy_out: endpoint {}; > + }; > + > + port@1 { > + reg = <1>; > + > + usb_1_ss0_qmpphy_usb_ss_in: endpoint {}; > + }; > + > + port@2 { > + reg = <2>; > + > + usb_1_ss0_qmpphy_dp_in: endpoint {}; Unless the configuration is dynamic or platform-dependent, please link DWC3, QMP PHY and DP nodes in the SoC.dtsi. > + }; > + }; > }; > > usb_1_ss1_hsphy: phy@fd9000 { > @@ -2583,6 +2606,29 @@ usb_1_ss1_qmpphy: phy@fda000 { > #phy-cells = <1>; > > status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + usb_1_ss1_qmpphy_out: endpoint {}; > + }; > + > + port@1 { > + reg = <1>; > + > + usb_1_ss1_qmpphy_usb_ss_in: endpoint {}; > + }; > + > + port@2 { > + reg = <2>; > + > + usb_1_ss1_qmpphy_dp_in: endpoint {}; > + }; > + }; > }; > > usb_1_ss2_hsphy: phy@fde000 { > @@ -2623,6 +2669,29 @@ usb_1_ss2_qmpphy: phy@fdf000 { > #phy-cells = <1>; > > status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + usb_1_ss2_qmpphy_out: endpoint {}; > + }; > + > + port@1 { > + reg = <1>; > + > + usb_1_ss2_qmpphy_usb_ss_in: endpoint {}; > + }; > + > + port@2 { > + reg = <2>; > + > + usb_1_ss2_qmpphy_dp_in: endpoint {}; > + }; > + }; > }; > > cnoc_main: interconnect@1500000 { > @@ -3445,8 +3514,22 @@ usb_1_ss2_dwc3: usb@a000000 { > > dma-coherent; > > - port { > - usb_1_ss2_role_switch: endpoint { > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + usb_1_ss2_dwc3_hs: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + usb_1_ss2_dwc3_ss: endpoint { > + }; > }; > }; > }; > @@ -3590,8 +3673,22 @@ usb_1_ss0_dwc3: usb@a600000 { > > dma-coherent; > > - port { > - usb_1_ss0_role_switch: endpoint { > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + usb_1_ss0_dwc3_hs: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + usb_1_ss0_dwc3_ss: endpoint { > + }; > }; > }; > }; > @@ -3673,8 +3770,22 @@ usb_1_ss1_dwc3: usb@a800000 { > > dma-coherent; > > - port { > - usb_1_ss1_role_switch: endpoint { > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + usb_1_ss1_dwc3_hs: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + usb_1_ss1_dwc3_ss: endpoint { > + }; > }; > }; > }; > > -- > 2.34.1 >
On 5/27/24 10:07, Abel Vesa wrote: > All PHYs, being QMP combo type, implement both USB and DP. Add the port > nodes for high-speed, super-speed and DP to all 3 PHYs belonging to > USB1. Also add the counterpart nodes for the DWC3 controllers. > > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- You can substitute this with https://lore.kernel.org/linux-arm-msm/20240512-typec-fix-sm8250-v4-8-ad153c747a97@linaro.org/ Konrad
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 5f90a0b3c016..63e85c5ea6c9 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2543,6 +2543,29 @@ usb_1_ss0_qmpphy: phy@fd5000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss0_qmpphy_out: endpoint {}; + }; + + port@1 { + reg = <1>; + + usb_1_ss0_qmpphy_usb_ss_in: endpoint {}; + }; + + port@2 { + reg = <2>; + + usb_1_ss0_qmpphy_dp_in: endpoint {}; + }; + }; }; usb_1_ss1_hsphy: phy@fd9000 { @@ -2583,6 +2606,29 @@ usb_1_ss1_qmpphy: phy@fda000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss1_qmpphy_out: endpoint {}; + }; + + port@1 { + reg = <1>; + + usb_1_ss1_qmpphy_usb_ss_in: endpoint {}; + }; + + port@2 { + reg = <2>; + + usb_1_ss1_qmpphy_dp_in: endpoint {}; + }; + }; }; usb_1_ss2_hsphy: phy@fde000 { @@ -2623,6 +2669,29 @@ usb_1_ss2_qmpphy: phy@fdf000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss2_qmpphy_out: endpoint {}; + }; + + port@1 { + reg = <1>; + + usb_1_ss2_qmpphy_usb_ss_in: endpoint {}; + }; + + port@2 { + reg = <2>; + + usb_1_ss2_qmpphy_dp_in: endpoint {}; + }; + }; }; cnoc_main: interconnect@1500000 { @@ -3445,8 +3514,22 @@ usb_1_ss2_dwc3: usb@a000000 { dma-coherent; - port { - usb_1_ss2_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss2_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss2_dwc3_ss: endpoint { + }; }; }; }; @@ -3590,8 +3673,22 @@ usb_1_ss0_dwc3: usb@a600000 { dma-coherent; - port { - usb_1_ss0_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss0_dwc3_ss: endpoint { + }; }; }; }; @@ -3673,8 +3770,22 @@ usb_1_ss1_dwc3: usb@a800000 { dma-coherent; - port { - usb_1_ss1_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss1_dwc3_ss: endpoint { + }; }; }; };
All PHYs, being QMP combo type, implement both USB and DP. Add the port nodes for high-speed, super-speed and DP to all 3 PHYs belonging to USB1. Also add the counterpart nodes for the DWC3 controllers. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 123 +++++++++++++++++++++++++++++++-- 1 file changed, 117 insertions(+), 6 deletions(-)