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Mon, 27 May 2024 01:07:40 -0700 (PDT) Received: from [127.0.1.1] ([188.27.161.69]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-579d30b82a8sm1240893a12.79.2024.05.27.01.07.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 May 2024 01:07:40 -0700 (PDT) From: Abel Vesa Date: Mon, 27 May 2024 11:07:27 +0300 Subject: [PATCH 1/3] arm64: dts: qcom: x1e80100: Add ports nodes to USB1 SS[0-2] PHYs and controllers Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240527-x1e80100-dts-pmic-glink-v1-1-7ea5c8eb4d2b@linaro.org> References: <20240527-x1e80100-dts-pmic-glink-v1-0-7ea5c8eb4d2b@linaro.org> In-Reply-To: <20240527-x1e80100-dts-pmic-glink-v1-0-7ea5c8eb4d2b@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE All PHYs, being QMP combo type, implement both USB and DP. Add the port nodes for high-speed, super-speed and DP to all 3 PHYs belonging to USB1. Also add the counterpart nodes for the DWC3 controllers. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 123 +++++++++++++++++++++++++++++++-- 1 file changed, 117 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 5f90a0b3c016..63e85c5ea6c9 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2543,6 +2543,29 @@ usb_1_ss0_qmpphy: phy@fd5000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss0_qmpphy_out: endpoint {}; + }; + + port@1 { + reg = <1>; + + usb_1_ss0_qmpphy_usb_ss_in: endpoint {}; + }; + + port@2 { + reg = <2>; + + usb_1_ss0_qmpphy_dp_in: endpoint {}; + }; + }; }; usb_1_ss1_hsphy: phy@fd9000 { @@ -2583,6 +2606,29 @@ usb_1_ss1_qmpphy: phy@fda000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss1_qmpphy_out: endpoint {}; + }; + + port@1 { + reg = <1>; + + usb_1_ss1_qmpphy_usb_ss_in: endpoint {}; + }; + + port@2 { + reg = <2>; + + usb_1_ss1_qmpphy_dp_in: endpoint {}; + }; + }; }; usb_1_ss2_hsphy: phy@fde000 { @@ -2623,6 +2669,29 @@ usb_1_ss2_qmpphy: phy@fdf000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss2_qmpphy_out: endpoint {}; + }; + + port@1 { + reg = <1>; + + usb_1_ss2_qmpphy_usb_ss_in: endpoint {}; + }; + + port@2 { + reg = <2>; + + usb_1_ss2_qmpphy_dp_in: endpoint {}; + }; + }; }; cnoc_main: interconnect@1500000 { @@ -3445,8 +3514,22 @@ usb_1_ss2_dwc3: usb@a000000 { dma-coherent; - port { - usb_1_ss2_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss2_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss2_dwc3_ss: endpoint { + }; }; }; }; @@ -3590,8 +3673,22 @@ usb_1_ss0_dwc3: usb@a600000 { dma-coherent; - port { - usb_1_ss0_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss0_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss0_dwc3_ss: endpoint { + }; }; }; }; @@ -3673,8 +3770,22 @@ usb_1_ss1_dwc3: usb@a800000 { dma-coherent; - port { - usb_1_ss1_role_switch: endpoint { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_ss1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_ss1_dwc3_ss: endpoint { + }; }; }; };