| Message ID | 20240530-x1e80100-dts-pcie6a-v1-1-ee17a9939ba5@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | arm64: dts: qcom: x1e80100: Add proper support for NVMe (PCIe 6a) | expand |
On Thu, May 30, 2024 at 06:43:39PM +0300, Abel Vesa wrote: > The actual PHY regulator is L1d instead of L3j, so fix it accordingly. > > Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support") > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On Thu, May 30, 2024 at 06:43:39PM +0300, Abel Vesa wrote: > The actual PHY regulator is L1d instead of L3j, so fix it accordingly. > > Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support") This patch and the next one is missing a CC stable tag: Cc: stable@vger.kernel.org # 6.9 > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Johan
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts index ed8b80627534..3ce2c8a841ec 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts @@ -659,7 +659,7 @@ &pcie6a { }; &pcie6a_phy { - vdda-phy-supply = <&vreg_l3j_0p8>; + vdda-phy-supply = <&vreg_l1d_0p8>; vdda-pll-supply = <&vreg_l2j_1p2>; status = "okay";
The actual PHY regulator is L1d instead of L3j, so fix it accordingly. Fixes: d7e03cce0400 ("arm64: dts: qcom: x1e80100-crd: Enable more support") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)