| Message ID | 20240531090249.10293-4-quic_tdas@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for SA8775P Multimedia clock controllers | expand |
On 31/05/2024 11:02, Taniya Das wrote: > Set FORCE_MEM_CORE_ON bit for gcc_ufs_phy_ice_core_clk. Why? > > Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") What bug are you fixing? Best regards, Krzysztof
On 5/31/2024 3:27 PM, Krzysztof Kozlowski wrote: > On 31/05/2024 11:02, Taniya Das wrote: >> Set FORCE_MEM_CORE_ON bit for gcc_ufs_phy_ice_core_clk. > > Why? > Yes, my bad I didn't update the commit text for this series. Force mem core bit for UFS ICE clock is required to retain the logic in memories of the subsystem across power states. Will update the commit text with these details in next series. >> >> Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") > > What bug are you fixing? > > > Best regards, > Krzysztof >
diff --git a/drivers/clk/qcom/gcc-sa8775p.c b/drivers/clk/qcom/gcc-sa8775p.c index 71fa95f59a0a..23b5207dc606 100644 --- a/drivers/clk/qcom/gcc-sa8775p.c +++ b/drivers/clk/qcom/gcc-sa8775p.c @@ -4686,6 +4686,9 @@ static int gcc_sa8775p_probe(struct platform_device *pdev) qcom_branch_set_clk_en(regmap, 0x34004); /* GCC_VIDEO_AHB_CLK */ qcom_branch_set_clk_en(regmap, 0x34024); /* GCC_VIDEO_XO_CLK */ + /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ + qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); + return qcom_cc_really_probe(pdev, &gcc_sa8775p_desc, regmap); }
Set FORCE_MEM_CORE_ON bit for gcc_ufs_phy_ice_core_clk. Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p") Signed-off-by: Taniya Das <quic_tdas@quicinc.com> --- drivers/clk/qcom/gcc-sa8775p.c | 3 +++ 1 file changed, 3 insertions(+)