| Message ID | 20240605-x1e80100-pci-bindings-fix-v2-1-c465e87966fc@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [v2] dt-bindings: PCI: qcom: x1e80100: Make the MHI reg region mandatory | expand |
On 05/06/2024 10:19, Abel Vesa wrote: > All PCIe controllers found on X1E80100 have MHI register region. > So change the schema to reflect that. > > Fixes: 692eadd51698 ("dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller") > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > Note that this patch will trigger an MHI reg region > warning until the following patch will also be merged: > > https://lore.kernel.org/all/20240604-x1e80100-dts-fixes-pcie6a-v2-1-0b4d8c6256e5@linaro.org/ > --- > Changes in v2: > - Dropped the vddpe supply change as that will have to be reworked > in a different way, maybe on multiple platforms. > - Added SoC name to the subject line > - Link to v1: https://lore.kernel.org/r/20240604-x1e80100-pci-bindings-fix-v1-1-f4e20251b3d0@linaro.org > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Wed, Jun 05, 2024 at 11:19:01AM +0300, Abel Vesa wrote: > All PCIe controllers found on X1E80100 have MHI register region. > So change the schema to reflect that. > > Fixes: 692eadd51698 ("dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller") > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > Note that this patch will trigger an MHI reg region > warning until the following patch will also be merged: > > https://lore.kernel.org/all/20240604-x1e80100-dts-fixes-pcie6a-v2-1-0b4d8c6256e5@linaro.org/ > --- > Changes in v2: > - Dropped the vddpe supply change as that will have to be reworked > in a different way, maybe on multiple platforms. > - Added SoC name to the subject line > - Link to v1: https://lore.kernel.org/r/20240604-x1e80100-pci-bindings-fix-v1-1-f4e20251b3d0@linaro.org > --- > Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml > index 1074310a8e7a..a9db0a231563 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml > @@ -19,11 +19,10 @@ properties: > const: qcom,pcie-x1e80100 > > reg: > - minItems: 5 > + minItems: 6 > maxItems: 6 > > reg-names: > - minItems: 5 > items: > - const: parf # Qualcomm specific registers > - const: dbi # DesignWare PCIe registers > > --- > base-commit: d97496ca23a2d4ee80b7302849404859d9058bcd > change-id: 20240604-x1e80100-pci-bindings-fix-196925d15260 > > Best regards, > -- > Abel Vesa <abel.vesa@linaro.org> >
On Wed, 05 Jun 2024 11:19:01 +0300, Abel Vesa wrote: > All PCIe controllers found on X1E80100 have MHI register region. > So change the schema to reflect that. > > Fixes: 692eadd51698 ("dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller") > Signed-off-by: Abel Vesa <abel.vesa@linaro.org> > --- > Note that this patch will trigger an MHI reg region > warning until the following patch will also be merged: > > https://lore.kernel.org/all/20240604-x1e80100-dts-fixes-pcie6a-v2-1-0b4d8c6256e5@linaro.org/ > --- > Changes in v2: > - Dropped the vddpe supply change as that will have to be reworked > in a different way, maybe on multiple platforms. > - Added SoC name to the subject line > - Link to v1: https://lore.kernel.org/r/20240604-x1e80100-pci-bindings-fix-v1-1-f4e20251b3d0@linaro.org > --- > Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Hello, > All PCIe controllers found on X1E80100 have MHI register region. > So change the schema to reflect that. Applied to dt-bindings, thank you! [1/1] dt-bindings: PCI: qcom: x1e80100: Make the MHI reg region mandatory https://git.kernel.org/pci/pci/c/30e7c6cc88b0 Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml index 1074310a8e7a..a9db0a231563 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml @@ -19,11 +19,10 @@ properties: const: qcom,pcie-x1e80100 reg: - minItems: 5 + minItems: 6 maxItems: 6 reg-names: - minItems: 5 items: - const: parf # Qualcomm specific registers - const: dbi # DesignWare PCIe registers
All PCIe controllers found on X1E80100 have MHI register region. So change the schema to reflect that. Fixes: 692eadd51698 ("dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> --- Note that this patch will trigger an MHI reg region warning until the following patch will also be merged: https://lore.kernel.org/all/20240604-x1e80100-dts-fixes-pcie6a-v2-1-0b4d8c6256e5@linaro.org/ --- Changes in v2: - Dropped the vddpe supply change as that will have to be reworked in a different way, maybe on multiple platforms. - Added SoC name to the subject line - Link to v1: https://lore.kernel.org/r/20240604-x1e80100-pci-bindings-fix-v1-1-f4e20251b3d0@linaro.org --- Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) --- base-commit: d97496ca23a2d4ee80b7302849404859d9058bcd change-id: 20240604-x1e80100-pci-bindings-fix-196925d15260 Best regards,