| Message ID | 20240607113445.2909-1-quic_kbajaj@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | arm64: dts: qcom: qdu1000: Add secure qfprom node | expand |
On Fri, Jun 07, 2024 at 05:04:45PM +0530, Komal Bajaj wrote: > Add secure qfprom node and also add properties for multi channel > DDR. This will be required for LLCC driver to pick the correct > LLCC configuration. 'will be' or 'is' ? > > Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> > --- > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > index 7a77f7a55498..d8df1bab63d5 100644 > --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi > +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > @@ -1584,6 +1584,21 @@ system-cache-controller@19200000 { > reg-names = "llcc0_base", > "llcc_broadcast_base"; > interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; > + > + nvmem-cell-names = "multi-chan-ddr"; > + nvmem-cells = <&multi_chan_ddr>; > + }; > + > + sec_qfprom: efuse@221c8000 { > + compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom"; > + reg = <0 0x221c8000 0 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + multi_chan_ddr: multi-chan-ddr@12b { > + reg = <0x12b 0x1>; > + bits = <0 2>; > + }; > }; > }; > > -- > 2.42.0 >
On 6/7/2024 5:22 PM, Dmitry Baryshkov wrote: > On Fri, Jun 07, 2024 at 05:04:45PM +0530, Komal Bajaj wrote: >> Add secure qfprom node and also add properties for multi channel >> DDR. This will be required for LLCC driver to pick the correct >> LLCC configuration. > > > 'will be' or 'is' ? Sure, will update like that. Thanks Komal > >> >> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 15 +++++++++++++++ >> 1 file changed, 15 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> index 7a77f7a55498..d8df1bab63d5 100644 >> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi >> @@ -1584,6 +1584,21 @@ system-cache-controller@19200000 { >> reg-names = "llcc0_base", >> "llcc_broadcast_base"; >> interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; >> + >> + nvmem-cell-names = "multi-chan-ddr"; >> + nvmem-cells = <&multi_chan_ddr>; >> + }; >> + >> + sec_qfprom: efuse@221c8000 { >> + compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom"; >> + reg = <0 0x221c8000 0 0x1000>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + multi_chan_ddr: multi-chan-ddr@12b { >> + reg = <0x12b 0x1>; >> + bits = <0 2>; >> + }; >> }; >> }; >> >> -- >> 2.42.0 >> >
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 7a77f7a55498..d8df1bab63d5 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1584,6 +1584,21 @@ system-cache-controller@19200000 { reg-names = "llcc0_base", "llcc_broadcast_base"; interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + + nvmem-cell-names = "multi-chan-ddr"; + nvmem-cells = <&multi_chan_ddr>; + }; + + sec_qfprom: efuse@221c8000 { + compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom"; + reg = <0 0x221c8000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + multi_chan_ddr: multi-chan-ddr@12b { + reg = <0x12b 0x1>; + bits = <0 2>; + }; }; };
Add secure qfprom node and also add properties for multi channel DDR. This will be required for LLCC driver to pick the correct LLCC configuration. Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) -- 2.42.0