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Fri, 14 Jun 2024 03:18:27 -0700 (PDT) Received: from umbar.lan ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-2ec05bf44c4sm5000241fa.9.2024.06.14.03.18.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Jun 2024 03:18:26 -0700 (PDT) From: Dmitry Baryshkov Date: Fri, 14 Jun 2024 13:18:24 +0300 Subject: [PATCH v3 1/5] phy: qcom: qmp-pcie: restore compatibility with existing DTs Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240614-fix-pcie-phy-compat-v3-1-730d1811acf4@linaro.org> References: <20240614-fix-pcie-phy-compat-v3-0-730d1811acf4@linaro.org> In-Reply-To: <20240614-fix-pcie-phy-compat-v3-0-730d1811acf4@linaro.org> To: Vinod Koul , Kishon Vijay Abraham I , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , devicetree@vger.kernel.org X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1592; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=T3DjvXEe+sumQ+ecA/DCNSeChO1xZMZY4sezj86K88Y=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBmbBjwWST2vn0/HBi504jSxpaS/FcGYEQXws/0Z Li9eCQgMTCJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZmwY8AAKCRCLPIo+Aiko 1SIhB/4inbA4gW2P2tS7P/P1h40jhnWYgOhODA3nURHZNRa2WbLmoL/QVHztCJmCBE/k+9E5BDX cmjO6e9MO2whENnZ/hCIXYdsnH26ykaSADDVq4w+ZdY4M6n61Ey8F0FWppsIjGEq7vFdD+ND1tr rvF9yZd1I3yXCuyCEzB/g8Y7WQkjW8qosq2/n1m973uV74+XHx9pXdP60YlaiDwkjdvS0Pb6wIv RQHgjSzBkZ2lH+YDnW0dnz6eCpdDsjTMgopujrOiScm3dzlFKcWJOmk+wskNoQQVO17/FVBvIaM FUhA9QYgbBiJ80/+mMos1OhMQby4ExOQnUYN5yth2ihXACUz X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Existing device trees specify only a single clock-output-name for the PCIe PHYs. The function phy_aux_clk_register() expects a second entry in that property. When it doesn't find it, it returns an error, thus failing the probe of the PHY and thus breaking support for the corresponding PCIe host. Follow the approach of the combo USB+DT PHY and generate the name for the AUX clocks instead of requiring it in DT. Fixes: 583ca9ccfa80 ("phy: qcom: qmp-pcie: register second optional PHY AUX clock") Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 8cb91b9114d6..5b36cc7ac78b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -4033,14 +4033,11 @@ static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np) { struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed; struct clk_init_data init = { }; - int ret; + char name[64]; - ret = of_property_read_string_index(np, "clock-output-names", 1, &init.name); - if (ret) { - dev_err(qmp->dev, "%pOFn: No clock-output-names index 1\n", np); - return ret; - } + snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev)); + init.name = name; init.ops = &clk_fixed_rate_ops; fixed->fixed_rate = qmp->cfg->aux_clock_rate;