From patchwork Thu Jun 20 08:14:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Varadarajan Narayanan X-Patchwork-Id: 13704941 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 839BC17D8A9; Thu, 20 Jun 2024 08:15:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718871335; cv=none; b=Pl9jQsTHu6N7P98tOxiM/3acaOxXzeqnQ+cR/0hNsShub7J43fdD7Pv2KBrD+B1fcy4NTjqr5StDTYGVie+JXkrZ7NS0D7g6WMoThkgPwpTv5azC6R/WqnlzP9IQGrtt+RzcuuURpY4L5FevB+hmvN7b0/Ap5IvQF8npraNwx1U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718871335; c=relaxed/simple; bh=TxsvJ8OgBiodLCCdaLs2xApUQXZFe26E82HRP/a1U9w=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=W6HACRmRdwFaierVE4jzm/zom6vus5pFhxOlrGW9eWdVUfSNhJNIp7QZbULZgoQ8l5QdKTtKB5xVSthA4KPrx1Y4j0CE7uJjOZp6upnAEdgBVL93h6Hn4WmBa16cvEYuB7ob3sxOPBpylW7b9KWM3VDMDznWAyQSvRUQuz1LbBM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=YoJFSAti; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="YoJFSAti" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45JNp7pt025744; Thu, 20 Jun 2024 08:15:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= nhz2iTdkoqJ8YPTwnTRtpK/Svwj4ZcIoO75gG7Yjjiw=; b=YoJFSAtiE0h1/3LY bOj8Ix//Wec4l41ogtSldnbmMJOmxy4jMpS2srt8CJCwzl0lOYM9ket6LLkXSqsn PDlfbLv3EygpFpL42EdN6vL95t8yzoFBD5VtcNr25HpQyN2/r8EZMuVMpKHN8Gn5 keGnuiAJ/qY6CE3gB8c6yXK7CvNWiU4fssNMfK9t9r2d3Jiso319rPkzcRhhoJ/P pGkpi4eYorADTNfI4LfqiWJ5BJs9ZoB+ZhAz5E/gcwm+DwaYRxjUfb+ShY+nkAAs lUVrIe8rVmlg/QcjJJVrTnP1UUwliDWcDiSItPNOWZ3wLwCTP3yzb0Ah035m1Zb8 LU2Nmw== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3yujc4krnp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Jun 2024 08:15:21 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45K8FL6a018467 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 20 Jun 2024 08:15:21 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 20 Jun 2024 01:15:14 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v1 2/7] dt-bindings: soc: qcom: cpr3: Add bindings for IPQ9574 Date: Thu, 20 Jun 2024 13:44:22 +0530 Message-ID: <20240620081427.2860066-3-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240620081427.2860066-1-quic_varada@quicinc.com> References: <20240620081427.2860066-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: QGxXTVV3LoMcN45-bjhDnPyFuKvE7iWq X-Proofpoint-GUID: QGxXTVV3LoMcN45-bjhDnPyFuKvE7iWq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-20_04,2024-06-19_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 priorityscore=1501 mlxlogscore=999 malwarescore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2406200058 Add the bindings for the IPQ9574 CPR3 driver to the documentation. Signed-off-by: Varadarajan Narayanan --- .../bindings/soc/qcom/qcom,cpr3.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml index acf2e294866b..d5e02505c863 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml @@ -24,6 +24,7 @@ properties: - const: qcom,cpr4 - items: - enum: + - qcom,ipq9574-cprh - qcom,msm8998-cprh - qcom,sdm630-cprh - const: qcom,cprh @@ -52,9 +53,11 @@ properties: nvmem-cells: description: Cells containing the fuse corners and revision data + minItems: 17 maxItems: 32 nvmem-cell-names: + minItems: 17 maxItems: 32 operating-points-v2: true @@ -74,6 +77,35 @@ required: additionalProperties: false allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9574-cprh + then: + properties: + + nvmem-cell-names: + items: + - const: cpr_speed_bin + - const: cpr_fuse_revision + - const: cpr0_quotient1 + - const: cpr0_quotient2 + - const: cpr0_quotient3 + - const: cpr0_quotient4 + - const: cpr0_quotient_offset2 + - const: cpr0_quotient_offset3 + - const: cpr0_quotient_offset4 + - const: cpr0_init_voltage1 + - const: cpr0_init_voltage2 + - const: cpr0_init_voltage3 + - const: cpr0_init_voltage4 + - const: cpr0_ring_osc1 + - const: cpr0_ring_osc2 + - const: cpr0_ring_osc3 + - const: cpr0_ring_osc4 + - if: properties: compatible: