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Wed, 26 Jun 2024 12:38:07 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 26 Jun 2024 05:38:01 -0700 From: Krishna chaitanya chundru Date: Wed, 26 Jun 2024 18:07:50 +0530 Subject: [PATCH RFC 2/7] arm64: dts: qcom: qcs6490-rb3gen2: Add qps615 node Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240626-qps615-v1-2-2ade7bd91e02@quicinc.com> References: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> In-Reply-To: <20240626-qps615-v1-0-2ade7bd91e02@quicinc.com> To: Bartosz Golaszewski , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Jingoo Han CC: , , , , , , , Krishna chaitanya chundru X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; a=ed25519-sha256; t=1719405471; l=2284; i=quic_krichai@quicinc.com; s=20230907; h=from:subject:message-id; bh=fCGQL2xdobFoV3TOvDGNRKzN4TKnBTgn6hF+FGAUroQ=; b=iPb1zkL3JhQOr0EuK2Hs0IBtLEUHOCintbcdEjclceLnh/TI3R0Igd35M10YpeSqu0JXdI/Jd oXj2HbY7m+FDxmPNPsAqgabNRB0sbvB9ZzgJ8hbhLRL/yA+nFc98RG1 X-Developer-Key: i=quic_krichai@quicinc.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: WLdN2Rdh0IBG9-9jf96eKCkJRtAOZ2nE X-Proofpoint-ORIG-GUID: WLdN2Rdh0IBG9-9jf96eKCkJRtAOZ2nE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-26_07,2024-06-25_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 phishscore=0 mlxlogscore=978 bulkscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2406140001 definitions=main-2406260094 QPS615 switch power is controlled by GPIO's. Once the GPIO's are enabled, switch power will be on. Make all GPIO's as fixed regulators and inter link them so that enabling the regulator will enable power to the switch by enabling GPIO's. Enable i2c0 which is required to configure the switch. Signed-off-by: Krishna chaitanya chundru --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 55 ++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index a085ff5b5fb2..5b453896a6c9 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -511,6 +511,61 @@ vreg_bob_3p296: bob { regulator-max-microvolt = <3960000>; }; }; + + qps615_0p9_vreg: qps615-0p9-vreg { + compatible = "regulator-fixed"; + regulator-name = "qps615_0p9_vreg"; + gpio = <&pm8350c_gpios 2 0>; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + enable-active-high; + regulator-enable-ramp-delay = <4300>; + }; + + qps615_1p8_vreg: qps615-1p8-vreg { + compatible = "regulator-fixed"; + regulator-name = "qps615_1p8_vreg"; + gpio = <&pm8350c_gpios 3 0>; + vin-supply = <&qps615_0p9_vreg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-enable-ramp-delay = <10000>; + }; + + qps615_rsex_vreg: qps615-rsex-vreg { + compatible = "regulator-fixed"; + regulator-name = "qps615_rsex_vreg"; + gpio = <&pm8350c_gpios 1 0>; + vin-supply = <&qps615_1p8_vreg>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-enable-ramp-delay = <10000>; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&pcie1 { + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x01 0xff>; + + qps615@0 { + compatible = "pci1179,0623"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + vdda-supply = <&qps615_rsex_vreg>; + switch-i2c-cntrl = <&i2c0>; + }; + }; }; &gcc {