| Message ID | 20240717-dispcc-sm8550-fixes-v2-3-5c4a3128c40b@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | eb64ccacd0cd9343926424f63fec76e73eb815a7 |
| Headers | show |
| Series | clk: qcom: merge SM8550 and SM8650 display clock controller drivers | expand |
On 17/07/2024 12:04, Dmitry Baryshkov wrote: > The clk_init_data instances are not changed at runtime. Mark them as > constant data. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/clk/qcom/dispcc-sm8550.c | 160 +++++++++++++++++++-------------------- > 1 file changed, 80 insertions(+), 80 deletions(-) > > diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c > index a98230540782..1604a6a4acdc 100644 > --- a/drivers/clk/qcom/dispcc-sm8550.c > +++ b/drivers/clk/qcom/dispcc-sm8550.c > @@ -95,7 +95,7 @@ static struct clk_alpha_pll disp_cc_pll0 = { > .num_vco = ARRAY_SIZE(lucid_ole_vco), > .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > .clkr = { > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_pll0", > .parent_data = &(const struct clk_parent_data) { > .index = DT_BI_TCXO, > @@ -126,7 +126,7 @@ static struct clk_alpha_pll disp_cc_pll1 = { > .num_vco = ARRAY_SIZE(lucid_ole_vco), > .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], > .clkr = { > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_pll1", > .parent_data = &(const struct clk_parent_data) { > .index = DT_BI_TCXO, > @@ -286,7 +286,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_6, > .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_ahb_clk_src", > .parent_data = disp_cc_parent_data_6, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), > @@ -306,7 +306,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_2, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_byte0_clk_src", > .parent_data = disp_cc_parent_data_2, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), > @@ -321,7 +321,7 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_2, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_byte1_clk_src", > .parent_data = disp_cc_parent_data_2, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), > @@ -336,7 +336,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_0, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_aux_clk_src", > .parent_data = disp_cc_parent_data_0, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > @@ -350,7 +350,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_7, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_link_clk_src", > .parent_data = disp_cc_parent_data_7, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), > @@ -365,7 +365,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_4, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_pixel0_clk_src", > .parent_data = disp_cc_parent_data_4, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), > @@ -380,7 +380,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_4, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_pixel1_clk_src", > .parent_data = disp_cc_parent_data_4, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), > @@ -395,7 +395,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_0, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_aux_clk_src", > .parent_data = disp_cc_parent_data_0, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > @@ -409,7 +409,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_3, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_link_clk_src", > .parent_data = disp_cc_parent_data_3, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > @@ -424,7 +424,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_1, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_pixel0_clk_src", > .parent_data = disp_cc_parent_data_1, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > @@ -439,7 +439,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_1, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_pixel1_clk_src", > .parent_data = disp_cc_parent_data_1, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > @@ -454,7 +454,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_0, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx2_aux_clk_src", > .parent_data = disp_cc_parent_data_0, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > @@ -468,7 +468,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_3, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx2_link_clk_src", > .parent_data = disp_cc_parent_data_3, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > @@ -483,7 +483,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_1, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx2_pixel0_clk_src", > .parent_data = disp_cc_parent_data_1, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > @@ -498,7 +498,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_1, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx2_pixel1_clk_src", > .parent_data = disp_cc_parent_data_1, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > @@ -513,7 +513,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_0, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx3_aux_clk_src", > .parent_data = disp_cc_parent_data_0, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > @@ -527,7 +527,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_3, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx3_link_clk_src", > .parent_data = disp_cc_parent_data_3, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > @@ -542,7 +542,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_1, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx3_pixel0_clk_src", > .parent_data = disp_cc_parent_data_1, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), > @@ -557,7 +557,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_5, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_esc0_clk_src", > .parent_data = disp_cc_parent_data_5, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), > @@ -572,7 +572,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_5, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_esc1_clk_src", > .parent_data = disp_cc_parent_data_5, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), > @@ -600,7 +600,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_8, > .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_mdp_clk_src", > .parent_data = disp_cc_parent_data_8, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_8), > @@ -615,7 +615,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_2, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_pclk0_clk_src", > .parent_data = disp_cc_parent_data_2, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), > @@ -630,7 +630,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_2, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_pclk1_clk_src", > .parent_data = disp_cc_parent_data_2, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), > @@ -645,7 +645,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_0, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_vsync_clk_src", > .parent_data = disp_cc_parent_data_0, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > @@ -665,7 +665,7 @@ static struct clk_rcg2 disp_cc_sleep_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_9, > .freq_tbl = ftbl_disp_cc_sleep_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_sleep_clk_src", > .parent_data = disp_cc_parent_data_9, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_9), > @@ -680,7 +680,7 @@ static struct clk_rcg2 disp_cc_xo_clk_src = { > .hid_width = 5, > .parent_map = disp_cc_parent_map_0, > .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_xo_clk_src", > .parent_data = disp_cc_parent_data_0_ao, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao), > @@ -693,7 +693,7 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { > .reg = 0x8120, > .shift = 0, > .width = 4, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_byte0_div_clk_src", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_byte0_clk_src.clkr.hw, > @@ -707,7 +707,7 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { > .reg = 0x813c, > .shift = 0, > .width = 4, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_byte1_div_clk_src", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_byte1_clk_src.clkr.hw, > @@ -721,7 +721,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { > .reg = 0x8188, > .shift = 0, > .width = 4, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_link_div_clk_src", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, > @@ -736,7 +736,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { > .reg = 0x821c, > .shift = 0, > .width = 4, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_link_div_clk_src", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, > @@ -751,7 +751,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { > .reg = 0x8250, > .shift = 0, > .width = 4, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx2_link_div_clk_src", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, > @@ -766,7 +766,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { > .reg = 0x82cc, > .shift = 0, > .width = 4, > - .clkr.hw.init = &(struct clk_init_data) { > + .clkr.hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx3_link_div_clk_src", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, > @@ -783,7 +783,7 @@ static struct clk_branch disp_cc_mdss_accu_clk = { > .clkr = { > .enable_reg = 0xe058, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data){ > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_accu_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_xo_clk_src.clkr.hw, > @@ -801,7 +801,7 @@ static struct clk_branch disp_cc_mdss_ahb1_clk = { > .clkr = { > .enable_reg = 0xa020, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_ahb1_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_ahb_clk_src.clkr.hw, > @@ -819,7 +819,7 @@ static struct clk_branch disp_cc_mdss_ahb_clk = { > .clkr = { > .enable_reg = 0x80a4, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_ahb_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_ahb_clk_src.clkr.hw, > @@ -837,7 +837,7 @@ static struct clk_branch disp_cc_mdss_byte0_clk = { > .clkr = { > .enable_reg = 0x8028, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_byte0_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_byte0_clk_src.clkr.hw, > @@ -855,7 +855,7 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = { > .clkr = { > .enable_reg = 0x802c, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_byte0_intf_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_byte0_div_clk_src.clkr.hw, > @@ -873,7 +873,7 @@ static struct clk_branch disp_cc_mdss_byte1_clk = { > .clkr = { > .enable_reg = 0x8030, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_byte1_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_byte1_clk_src.clkr.hw, > @@ -891,7 +891,7 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = { > .clkr = { > .enable_reg = 0x8034, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_byte1_intf_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_byte1_div_clk_src.clkr.hw, > @@ -909,7 +909,7 @@ static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { > .clkr = { > .enable_reg = 0x8058, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_aux_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, > @@ -927,7 +927,7 @@ static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { > .clkr = { > .enable_reg = 0x804c, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_crypto_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, > @@ -945,7 +945,7 @@ static struct clk_branch disp_cc_mdss_dptx0_link_clk = { > .clkr = { > .enable_reg = 0x8040, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_link_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, > @@ -963,7 +963,7 @@ static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { > .clkr = { > .enable_reg = 0x8048, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_link_intf_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, > @@ -981,7 +981,7 @@ static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { > .clkr = { > .enable_reg = 0x8050, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_pixel0_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, > @@ -999,7 +999,7 @@ static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { > .clkr = { > .enable_reg = 0x8054, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_pixel1_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, > @@ -1017,7 +1017,7 @@ static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { > .clkr = { > .enable_reg = 0x8044, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, > @@ -1035,7 +1035,7 @@ static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { > .clkr = { > .enable_reg = 0x8074, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_aux_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, > @@ -1053,7 +1053,7 @@ static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = { > .clkr = { > .enable_reg = 0x8070, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_crypto_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, > @@ -1071,7 +1071,7 @@ static struct clk_branch disp_cc_mdss_dptx1_link_clk = { > .clkr = { > .enable_reg = 0x8064, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_link_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, > @@ -1089,7 +1089,7 @@ static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { > .clkr = { > .enable_reg = 0x806c, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_link_intf_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, > @@ -1107,7 +1107,7 @@ static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { > .clkr = { > .enable_reg = 0x805c, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_pixel0_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, > @@ -1125,7 +1125,7 @@ static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { > .clkr = { > .enable_reg = 0x8060, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_pixel1_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, > @@ -1143,7 +1143,7 @@ static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { > .clkr = { > .enable_reg = 0x8068, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, > @@ -1161,7 +1161,7 @@ static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { > .clkr = { > .enable_reg = 0x808c, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx2_aux_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, > @@ -1179,7 +1179,7 @@ static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = { > .clkr = { > .enable_reg = 0x8088, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx2_crypto_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, > @@ -1197,7 +1197,7 @@ static struct clk_branch disp_cc_mdss_dptx2_link_clk = { > .clkr = { > .enable_reg = 0x8080, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx2_link_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, > @@ -1215,7 +1215,7 @@ static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { > .clkr = { > .enable_reg = 0x8084, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx2_link_intf_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, > @@ -1233,7 +1233,7 @@ static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { > .clkr = { > .enable_reg = 0x8078, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx2_pixel0_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, > @@ -1251,7 +1251,7 @@ static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { > .clkr = { > .enable_reg = 0x807c, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx2_pixel1_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, > @@ -1269,7 +1269,7 @@ static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { > .clkr = { > .enable_reg = 0x809c, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx3_aux_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, > @@ -1287,7 +1287,7 @@ static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = { > .clkr = { > .enable_reg = 0x80a0, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx3_crypto_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, > @@ -1305,7 +1305,7 @@ static struct clk_branch disp_cc_mdss_dptx3_link_clk = { > .clkr = { > .enable_reg = 0x8094, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx3_link_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, > @@ -1323,7 +1323,7 @@ static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { > .clkr = { > .enable_reg = 0x8098, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx3_link_intf_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, > @@ -1341,7 +1341,7 @@ static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { > .clkr = { > .enable_reg = 0x8090, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_dptx3_pixel0_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, > @@ -1359,7 +1359,7 @@ static struct clk_branch disp_cc_mdss_esc0_clk = { > .clkr = { > .enable_reg = 0x8038, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_esc0_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_esc0_clk_src.clkr.hw, > @@ -1377,7 +1377,7 @@ static struct clk_branch disp_cc_mdss_esc1_clk = { > .clkr = { > .enable_reg = 0x803c, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_esc1_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_esc1_clk_src.clkr.hw, > @@ -1395,7 +1395,7 @@ static struct clk_branch disp_cc_mdss_mdp1_clk = { > .clkr = { > .enable_reg = 0xa004, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_mdp1_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_mdp_clk_src.clkr.hw, > @@ -1413,7 +1413,7 @@ static struct clk_branch disp_cc_mdss_mdp_clk = { > .clkr = { > .enable_reg = 0x800c, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_mdp_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_mdp_clk_src.clkr.hw, > @@ -1431,7 +1431,7 @@ static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { > .clkr = { > .enable_reg = 0xa010, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_mdp_lut1_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_mdp_clk_src.clkr.hw, > @@ -1449,7 +1449,7 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = { > .clkr = { > .enable_reg = 0x8018, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_mdp_lut_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_mdp_clk_src.clkr.hw, > @@ -1467,7 +1467,7 @@ static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { > .clkr = { > .enable_reg = 0xc004, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_non_gdsc_ahb_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_ahb_clk_src.clkr.hw, > @@ -1485,7 +1485,7 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = { > .clkr = { > .enable_reg = 0x8004, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_pclk0_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_pclk0_clk_src.clkr.hw, > @@ -1503,7 +1503,7 @@ static struct clk_branch disp_cc_mdss_pclk1_clk = { > .clkr = { > .enable_reg = 0x8008, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_pclk1_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_pclk1_clk_src.clkr.hw, > @@ -1521,7 +1521,7 @@ static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { > .clkr = { > .enable_reg = 0xc00c, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_rscc_ahb_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_ahb_clk_src.clkr.hw, > @@ -1539,7 +1539,7 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { > .clkr = { > .enable_reg = 0xc008, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_rscc_vsync_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_vsync_clk_src.clkr.hw, > @@ -1557,7 +1557,7 @@ static struct clk_branch disp_cc_mdss_vsync1_clk = { > .clkr = { > .enable_reg = 0xa01c, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_vsync1_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_vsync_clk_src.clkr.hw, > @@ -1575,7 +1575,7 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { > .clkr = { > .enable_reg = 0x8024, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_mdss_vsync_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_mdss_vsync_clk_src.clkr.hw, > @@ -1593,7 +1593,7 @@ static struct clk_branch disp_cc_sleep_clk = { > .clkr = { > .enable_reg = 0xe074, > .enable_mask = BIT(0), > - .hw.init = &(struct clk_init_data) { > + .hw.init = &(const struct clk_init_data) { > .name = "disp_cc_sleep_clk", > .parent_hws = (const struct clk_hw*[]) { > &disp_cc_sleep_clk_src.clkr.hw, > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c index a98230540782..1604a6a4acdc 100644 --- a/drivers/clk/qcom/dispcc-sm8550.c +++ b/drivers/clk/qcom/dispcc-sm8550.c @@ -95,7 +95,7 @@ static struct clk_alpha_pll disp_cc_pll0 = { .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr = { - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_pll0", .parent_data = &(const struct clk_parent_data) { .index = DT_BI_TCXO, @@ -126,7 +126,7 @@ static struct clk_alpha_pll disp_cc_pll1 = { .num_vco = ARRAY_SIZE(lucid_ole_vco), .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], .clkr = { - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_pll1", .parent_data = &(const struct clk_parent_data) { .index = DT_BI_TCXO, @@ -286,7 +286,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_6, .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_ahb_clk_src", .parent_data = disp_cc_parent_data_6, .num_parents = ARRAY_SIZE(disp_cc_parent_data_6), @@ -306,7 +306,7 @@ static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_2, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_byte0_clk_src", .parent_data = disp_cc_parent_data_2, .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), @@ -321,7 +321,7 @@ static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_2, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_byte1_clk_src", .parent_data = disp_cc_parent_data_2, .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), @@ -336,7 +336,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx0_aux_clk_src", .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), @@ -350,7 +350,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_7, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx0_link_clk_src", .parent_data = disp_cc_parent_data_7, .num_parents = ARRAY_SIZE(disp_cc_parent_data_7), @@ -365,7 +365,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_pixel0_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_4, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx0_pixel0_clk_src", .parent_data = disp_cc_parent_data_4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), @@ -380,7 +380,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_pixel1_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_4, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx0_pixel1_clk_src", .parent_data = disp_cc_parent_data_4, .num_parents = ARRAY_SIZE(disp_cc_parent_data_4), @@ -395,7 +395,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx1_aux_clk_src", .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), @@ -409,7 +409,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx1_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), @@ -424,7 +424,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_pixel0_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx1_pixel0_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), @@ -439,7 +439,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_pixel1_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx1_pixel1_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), @@ -454,7 +454,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx2_aux_clk_src", .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), @@ -468,7 +468,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx2_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), @@ -483,7 +483,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_pixel0_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx2_pixel0_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), @@ -498,7 +498,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_pixel1_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx2_pixel1_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), @@ -513,7 +513,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx3_aux_clk_src", .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), @@ -527,7 +527,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx3_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), @@ -542,7 +542,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_pixel0_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_1, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx3_pixel0_clk_src", .parent_data = disp_cc_parent_data_1, .num_parents = ARRAY_SIZE(disp_cc_parent_data_1), @@ -557,7 +557,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_5, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_esc0_clk_src", .parent_data = disp_cc_parent_data_5, .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), @@ -572,7 +572,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_5, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_esc1_clk_src", .parent_data = disp_cc_parent_data_5, .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), @@ -600,7 +600,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_8, .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_mdp_clk_src", .parent_data = disp_cc_parent_data_8, .num_parents = ARRAY_SIZE(disp_cc_parent_data_8), @@ -615,7 +615,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_2, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_pclk0_clk_src", .parent_data = disp_cc_parent_data_2, .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), @@ -630,7 +630,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_2, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_pclk1_clk_src", .parent_data = disp_cc_parent_data_2, .num_parents = ARRAY_SIZE(disp_cc_parent_data_2), @@ -645,7 +645,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_vsync_clk_src", .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), @@ -665,7 +665,7 @@ static struct clk_rcg2 disp_cc_sleep_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_9, .freq_tbl = ftbl_disp_cc_sleep_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_sleep_clk_src", .parent_data = disp_cc_parent_data_9, .num_parents = ARRAY_SIZE(disp_cc_parent_data_9), @@ -680,7 +680,7 @@ static struct clk_rcg2 disp_cc_xo_clk_src = { .hid_width = 5, .parent_map = disp_cc_parent_map_0, .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_xo_clk_src", .parent_data = disp_cc_parent_data_0_ao, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0_ao), @@ -693,7 +693,7 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { .reg = 0x8120, .shift = 0, .width = 4, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_byte0_div_clk_src", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_byte0_clk_src.clkr.hw, @@ -707,7 +707,7 @@ static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = { .reg = 0x813c, .shift = 0, .width = 4, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_byte1_div_clk_src", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_byte1_clk_src.clkr.hw, @@ -721,7 +721,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx0_link_div_clk_src = { .reg = 0x8188, .shift = 0, .width = 4, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx0_link_div_clk_src", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, @@ -736,7 +736,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx1_link_div_clk_src = { .reg = 0x821c, .shift = 0, .width = 4, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx1_link_div_clk_src", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, @@ -751,7 +751,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx2_link_div_clk_src = { .reg = 0x8250, .shift = 0, .width = 4, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx2_link_div_clk_src", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, @@ -766,7 +766,7 @@ static struct clk_regmap_div disp_cc_mdss_dptx3_link_div_clk_src = { .reg = 0x82cc, .shift = 0, .width = 4, - .clkr.hw.init = &(struct clk_init_data) { + .clkr.hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx3_link_div_clk_src", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, @@ -783,7 +783,7 @@ static struct clk_branch disp_cc_mdss_accu_clk = { .clkr = { .enable_reg = 0xe058, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_accu_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_xo_clk_src.clkr.hw, @@ -801,7 +801,7 @@ static struct clk_branch disp_cc_mdss_ahb1_clk = { .clkr = { .enable_reg = 0xa020, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_ahb1_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_ahb_clk_src.clkr.hw, @@ -819,7 +819,7 @@ static struct clk_branch disp_cc_mdss_ahb_clk = { .clkr = { .enable_reg = 0x80a4, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_ahb_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_ahb_clk_src.clkr.hw, @@ -837,7 +837,7 @@ static struct clk_branch disp_cc_mdss_byte0_clk = { .clkr = { .enable_reg = 0x8028, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_byte0_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_byte0_clk_src.clkr.hw, @@ -855,7 +855,7 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = { .clkr = { .enable_reg = 0x802c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_byte0_intf_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_byte0_div_clk_src.clkr.hw, @@ -873,7 +873,7 @@ static struct clk_branch disp_cc_mdss_byte1_clk = { .clkr = { .enable_reg = 0x8030, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_byte1_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_byte1_clk_src.clkr.hw, @@ -891,7 +891,7 @@ static struct clk_branch disp_cc_mdss_byte1_intf_clk = { .clkr = { .enable_reg = 0x8034, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_byte1_intf_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_byte1_div_clk_src.clkr.hw, @@ -909,7 +909,7 @@ static struct clk_branch disp_cc_mdss_dptx0_aux_clk = { .clkr = { .enable_reg = 0x8058, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx0_aux_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_aux_clk_src.clkr.hw, @@ -927,7 +927,7 @@ static struct clk_branch disp_cc_mdss_dptx0_crypto_clk = { .clkr = { .enable_reg = 0x804c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx0_crypto_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, @@ -945,7 +945,7 @@ static struct clk_branch disp_cc_mdss_dptx0_link_clk = { .clkr = { .enable_reg = 0x8040, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx0_link_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_link_clk_src.clkr.hw, @@ -963,7 +963,7 @@ static struct clk_branch disp_cc_mdss_dptx0_link_intf_clk = { .clkr = { .enable_reg = 0x8048, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx0_link_intf_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, @@ -981,7 +981,7 @@ static struct clk_branch disp_cc_mdss_dptx0_pixel0_clk = { .clkr = { .enable_reg = 0x8050, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx0_pixel0_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw, @@ -999,7 +999,7 @@ static struct clk_branch disp_cc_mdss_dptx0_pixel1_clk = { .clkr = { .enable_reg = 0x8054, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx0_pixel1_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw, @@ -1017,7 +1017,7 @@ static struct clk_branch disp_cc_mdss_dptx0_usb_router_link_intf_clk = { .clkr = { .enable_reg = 0x8044, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx0_usb_router_link_intf_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, @@ -1035,7 +1035,7 @@ static struct clk_branch disp_cc_mdss_dptx1_aux_clk = { .clkr = { .enable_reg = 0x8074, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx1_aux_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx1_aux_clk_src.clkr.hw, @@ -1053,7 +1053,7 @@ static struct clk_branch disp_cc_mdss_dptx1_crypto_clk = { .clkr = { .enable_reg = 0x8070, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx1_crypto_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, @@ -1071,7 +1071,7 @@ static struct clk_branch disp_cc_mdss_dptx1_link_clk = { .clkr = { .enable_reg = 0x8064, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx1_link_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx1_link_clk_src.clkr.hw, @@ -1089,7 +1089,7 @@ static struct clk_branch disp_cc_mdss_dptx1_link_intf_clk = { .clkr = { .enable_reg = 0x806c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx1_link_intf_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw, @@ -1107,7 +1107,7 @@ static struct clk_branch disp_cc_mdss_dptx1_pixel0_clk = { .clkr = { .enable_reg = 0x805c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx1_pixel0_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw, @@ -1125,7 +1125,7 @@ static struct clk_branch disp_cc_mdss_dptx1_pixel1_clk = { .clkr = { .enable_reg = 0x8060, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx1_pixel1_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw, @@ -1143,7 +1143,7 @@ static struct clk_branch disp_cc_mdss_dptx1_usb_router_link_intf_clk = { .clkr = { .enable_reg = 0x8068, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx1_usb_router_link_intf_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw, @@ -1161,7 +1161,7 @@ static struct clk_branch disp_cc_mdss_dptx2_aux_clk = { .clkr = { .enable_reg = 0x808c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx2_aux_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx2_aux_clk_src.clkr.hw, @@ -1179,7 +1179,7 @@ static struct clk_branch disp_cc_mdss_dptx2_crypto_clk = { .clkr = { .enable_reg = 0x8088, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx2_crypto_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, @@ -1197,7 +1197,7 @@ static struct clk_branch disp_cc_mdss_dptx2_link_clk = { .clkr = { .enable_reg = 0x8080, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx2_link_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx2_link_clk_src.clkr.hw, @@ -1215,7 +1215,7 @@ static struct clk_branch disp_cc_mdss_dptx2_link_intf_clk = { .clkr = { .enable_reg = 0x8084, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx2_link_intf_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx2_link_div_clk_src.clkr.hw, @@ -1233,7 +1233,7 @@ static struct clk_branch disp_cc_mdss_dptx2_pixel0_clk = { .clkr = { .enable_reg = 0x8078, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx2_pixel0_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx2_pixel0_clk_src.clkr.hw, @@ -1251,7 +1251,7 @@ static struct clk_branch disp_cc_mdss_dptx2_pixel1_clk = { .clkr = { .enable_reg = 0x807c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx2_pixel1_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx2_pixel1_clk_src.clkr.hw, @@ -1269,7 +1269,7 @@ static struct clk_branch disp_cc_mdss_dptx3_aux_clk = { .clkr = { .enable_reg = 0x809c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx3_aux_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx3_aux_clk_src.clkr.hw, @@ -1287,7 +1287,7 @@ static struct clk_branch disp_cc_mdss_dptx3_crypto_clk = { .clkr = { .enable_reg = 0x80a0, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx3_crypto_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, @@ -1305,7 +1305,7 @@ static struct clk_branch disp_cc_mdss_dptx3_link_clk = { .clkr = { .enable_reg = 0x8094, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx3_link_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx3_link_clk_src.clkr.hw, @@ -1323,7 +1323,7 @@ static struct clk_branch disp_cc_mdss_dptx3_link_intf_clk = { .clkr = { .enable_reg = 0x8098, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx3_link_intf_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx3_link_div_clk_src.clkr.hw, @@ -1341,7 +1341,7 @@ static struct clk_branch disp_cc_mdss_dptx3_pixel0_clk = { .clkr = { .enable_reg = 0x8090, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_dptx3_pixel0_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_dptx3_pixel0_clk_src.clkr.hw, @@ -1359,7 +1359,7 @@ static struct clk_branch disp_cc_mdss_esc0_clk = { .clkr = { .enable_reg = 0x8038, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_esc0_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_esc0_clk_src.clkr.hw, @@ -1377,7 +1377,7 @@ static struct clk_branch disp_cc_mdss_esc1_clk = { .clkr = { .enable_reg = 0x803c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_esc1_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_esc1_clk_src.clkr.hw, @@ -1395,7 +1395,7 @@ static struct clk_branch disp_cc_mdss_mdp1_clk = { .clkr = { .enable_reg = 0xa004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_mdp1_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_mdp_clk_src.clkr.hw, @@ -1413,7 +1413,7 @@ static struct clk_branch disp_cc_mdss_mdp_clk = { .clkr = { .enable_reg = 0x800c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_mdp_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_mdp_clk_src.clkr.hw, @@ -1431,7 +1431,7 @@ static struct clk_branch disp_cc_mdss_mdp_lut1_clk = { .clkr = { .enable_reg = 0xa010, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_mdp_lut1_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_mdp_clk_src.clkr.hw, @@ -1449,7 +1449,7 @@ static struct clk_branch disp_cc_mdss_mdp_lut_clk = { .clkr = { .enable_reg = 0x8018, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_mdp_lut_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_mdp_clk_src.clkr.hw, @@ -1467,7 +1467,7 @@ static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { .clkr = { .enable_reg = 0xc004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_non_gdsc_ahb_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_ahb_clk_src.clkr.hw, @@ -1485,7 +1485,7 @@ static struct clk_branch disp_cc_mdss_pclk0_clk = { .clkr = { .enable_reg = 0x8004, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_pclk0_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_pclk0_clk_src.clkr.hw, @@ -1503,7 +1503,7 @@ static struct clk_branch disp_cc_mdss_pclk1_clk = { .clkr = { .enable_reg = 0x8008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_pclk1_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_pclk1_clk_src.clkr.hw, @@ -1521,7 +1521,7 @@ static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { .clkr = { .enable_reg = 0xc00c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_rscc_ahb_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_ahb_clk_src.clkr.hw, @@ -1539,7 +1539,7 @@ static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { .clkr = { .enable_reg = 0xc008, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_rscc_vsync_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_vsync_clk_src.clkr.hw, @@ -1557,7 +1557,7 @@ static struct clk_branch disp_cc_mdss_vsync1_clk = { .clkr = { .enable_reg = 0xa01c, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_vsync1_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_vsync_clk_src.clkr.hw, @@ -1575,7 +1575,7 @@ static struct clk_branch disp_cc_mdss_vsync_clk = { .clkr = { .enable_reg = 0x8024, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_mdss_vsync_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_mdss_vsync_clk_src.clkr.hw, @@ -1593,7 +1593,7 @@ static struct clk_branch disp_cc_sleep_clk = { .clkr = { .enable_reg = 0xe074, .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data) { + .hw.init = &(const struct clk_init_data) { .name = "disp_cc_sleep_clk", .parent_hws = (const struct clk_hw*[]) { &disp_cc_sleep_clk_src.clkr.hw,
The clk_init_data instances are not changed at runtime. Mark them as constant data. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/dispcc-sm8550.c | 160 +++++++++++++++++++-------------------- 1 file changed, 80 insertions(+), 80 deletions(-)