| Message ID | 20240717-dispcc-sm8550-fixes-v2-7-5c4a3128c40b@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 99447ef003d199329c0a1890f54958fcd10f7063 |
| Headers | show |
| Series | clk: qcom: merge SM8550 and SM8650 display clock controller drivers | expand |
On 17/07/2024 12:04, Dmitry Baryshkov wrote: > The display clock controller indices for SM8650 and SM8550 are > completely equal. Replace the header file for qcom,sm8650-dispcc with > the symlink to the qcom,sm8550-dispcc header file. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > include/dt-bindings/clock/qcom,sm8650-dispcc.h | 103 +------------------------ > 1 file changed, 1 insertion(+), 102 deletions(-) > > diff --git a/include/dt-bindings/clock/qcom,sm8650-dispcc.h b/include/dt-bindings/clock/qcom,sm8650-dispcc.h > deleted file mode 100644 > index b0a668b395a5..000000000000 > --- a/include/dt-bindings/clock/qcom,sm8650-dispcc.h > +++ /dev/null > @@ -1,102 +0,0 @@ > -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > -/* > - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved > - * Copyright (c) 2023, Linaro Ltd. > - */ > - > -#ifndef _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H > -#define _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H > - > -/* DISP_CC clocks */ > -#define DISP_CC_MDSS_ACCU_CLK 0 > -#define DISP_CC_MDSS_AHB1_CLK 1 > -#define DISP_CC_MDSS_AHB_CLK 2 > -#define DISP_CC_MDSS_AHB_CLK_SRC 3 > -#define DISP_CC_MDSS_BYTE0_CLK 4 > -#define DISP_CC_MDSS_BYTE0_CLK_SRC 5 > -#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 > -#define DISP_CC_MDSS_BYTE0_INTF_CLK 7 > -#define DISP_CC_MDSS_BYTE1_CLK 8 > -#define DISP_CC_MDSS_BYTE1_CLK_SRC 9 > -#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10 > -#define DISP_CC_MDSS_BYTE1_INTF_CLK 11 > -#define DISP_CC_MDSS_DPTX0_AUX_CLK 12 > -#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13 > -#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 14 > -#define DISP_CC_MDSS_DPTX0_LINK_CLK 15 > -#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16 > -#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17 > -#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18 > -#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19 > -#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20 > -#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21 > -#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22 > -#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 23 > -#define DISP_CC_MDSS_DPTX1_AUX_CLK 24 > -#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 25 > -#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 26 > -#define DISP_CC_MDSS_DPTX1_LINK_CLK 27 > -#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 28 > -#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 29 > -#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 30 > -#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 31 > -#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 32 > -#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 33 > -#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 34 > -#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 35 > -#define DISP_CC_MDSS_DPTX2_AUX_CLK 36 > -#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 37 > -#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 38 > -#define DISP_CC_MDSS_DPTX2_LINK_CLK 39 > -#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40 > -#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41 > -#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42 > -#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43 > -#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44 > -#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45 > -#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46 > -#define DISP_CC_MDSS_DPTX3_AUX_CLK 47 > -#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48 > -#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 49 > -#define DISP_CC_MDSS_DPTX3_LINK_CLK 50 > -#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 51 > -#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 52 > -#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 53 > -#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 54 > -#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 55 > -#define DISP_CC_MDSS_ESC0_CLK 56 > -#define DISP_CC_MDSS_ESC0_CLK_SRC 57 > -#define DISP_CC_MDSS_ESC1_CLK 58 > -#define DISP_CC_MDSS_ESC1_CLK_SRC 59 > -#define DISP_CC_MDSS_MDP1_CLK 60 > -#define DISP_CC_MDSS_MDP_CLK 61 > -#define DISP_CC_MDSS_MDP_CLK_SRC 62 > -#define DISP_CC_MDSS_MDP_LUT1_CLK 63 > -#define DISP_CC_MDSS_MDP_LUT_CLK 64 > -#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 65 > -#define DISP_CC_MDSS_PCLK0_CLK 66 > -#define DISP_CC_MDSS_PCLK0_CLK_SRC 67 > -#define DISP_CC_MDSS_PCLK1_CLK 68 > -#define DISP_CC_MDSS_PCLK1_CLK_SRC 69 > -#define DISP_CC_MDSS_RSCC_AHB_CLK 70 > -#define DISP_CC_MDSS_RSCC_VSYNC_CLK 71 > -#define DISP_CC_MDSS_VSYNC1_CLK 72 > -#define DISP_CC_MDSS_VSYNC_CLK 73 > -#define DISP_CC_MDSS_VSYNC_CLK_SRC 74 > -#define DISP_CC_PLL0 75 > -#define DISP_CC_PLL1 76 > -#define DISP_CC_SLEEP_CLK 77 > -#define DISP_CC_SLEEP_CLK_SRC 78 > -#define DISP_CC_XO_CLK 79 > -#define DISP_CC_XO_CLK_SRC 80 > - > -/* DISP_CC resets */ > -#define DISP_CC_MDSS_CORE_BCR 0 > -#define DISP_CC_MDSS_CORE_INT2_BCR 1 > -#define DISP_CC_MDSS_RSCC_BCR 2 > - > -/* DISP_CC GDSCR */ > -#define MDSS_GDSC 0 > -#define MDSS_INT2_GDSC 1 > - > -#endif > diff --git a/include/dt-bindings/clock/qcom,sm8650-dispcc.h b/include/dt-bindings/clock/qcom,sm8650-dispcc.h > new file mode 120000 > index 000000000000..c0a291188f28 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,sm8650-dispcc.h > @@ -0,0 +1 @@ > +qcom,sm8550-dispcc.h > \ No newline at end of file > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On 17/07/2024 12:04, Dmitry Baryshkov wrote: > The display clock controller indices for SM8650 and SM8550 are > completely equal. Replace the header file for qcom,sm8650-dispcc with > the symlink to the qcom,sm8550-dispcc header file. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/include/dt-bindings/clock/qcom,sm8650-dispcc.h b/include/dt-bindings/clock/qcom,sm8650-dispcc.h deleted file mode 100644 index b0a668b395a5..000000000000 --- a/include/dt-bindings/clock/qcom,sm8650-dispcc.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved - * Copyright (c) 2023, Linaro Ltd. - */ - -#ifndef _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H -#define _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H - -/* DISP_CC clocks */ -#define DISP_CC_MDSS_ACCU_CLK 0 -#define DISP_CC_MDSS_AHB1_CLK 1 -#define DISP_CC_MDSS_AHB_CLK 2 -#define DISP_CC_MDSS_AHB_CLK_SRC 3 -#define DISP_CC_MDSS_BYTE0_CLK 4 -#define DISP_CC_MDSS_BYTE0_CLK_SRC 5 -#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6 -#define DISP_CC_MDSS_BYTE0_INTF_CLK 7 -#define DISP_CC_MDSS_BYTE1_CLK 8 -#define DISP_CC_MDSS_BYTE1_CLK_SRC 9 -#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10 -#define DISP_CC_MDSS_BYTE1_INTF_CLK 11 -#define DISP_CC_MDSS_DPTX0_AUX_CLK 12 -#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13 -#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 14 -#define DISP_CC_MDSS_DPTX0_LINK_CLK 15 -#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 16 -#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 17 -#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 18 -#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 19 -#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 20 -#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 21 -#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 22 -#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 23 -#define DISP_CC_MDSS_DPTX1_AUX_CLK 24 -#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 25 -#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 26 -#define DISP_CC_MDSS_DPTX1_LINK_CLK 27 -#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 28 -#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 29 -#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 30 -#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 31 -#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 32 -#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 33 -#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 34 -#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 35 -#define DISP_CC_MDSS_DPTX2_AUX_CLK 36 -#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 37 -#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 38 -#define DISP_CC_MDSS_DPTX2_LINK_CLK 39 -#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40 -#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41 -#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42 -#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43 -#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44 -#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45 -#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46 -#define DISP_CC_MDSS_DPTX3_AUX_CLK 47 -#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48 -#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 49 -#define DISP_CC_MDSS_DPTX3_LINK_CLK 50 -#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 51 -#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 52 -#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 53 -#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 54 -#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 55 -#define DISP_CC_MDSS_ESC0_CLK 56 -#define DISP_CC_MDSS_ESC0_CLK_SRC 57 -#define DISP_CC_MDSS_ESC1_CLK 58 -#define DISP_CC_MDSS_ESC1_CLK_SRC 59 -#define DISP_CC_MDSS_MDP1_CLK 60 -#define DISP_CC_MDSS_MDP_CLK 61 -#define DISP_CC_MDSS_MDP_CLK_SRC 62 -#define DISP_CC_MDSS_MDP_LUT1_CLK 63 -#define DISP_CC_MDSS_MDP_LUT_CLK 64 -#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 65 -#define DISP_CC_MDSS_PCLK0_CLK 66 -#define DISP_CC_MDSS_PCLK0_CLK_SRC 67 -#define DISP_CC_MDSS_PCLK1_CLK 68 -#define DISP_CC_MDSS_PCLK1_CLK_SRC 69 -#define DISP_CC_MDSS_RSCC_AHB_CLK 70 -#define DISP_CC_MDSS_RSCC_VSYNC_CLK 71 -#define DISP_CC_MDSS_VSYNC1_CLK 72 -#define DISP_CC_MDSS_VSYNC_CLK 73 -#define DISP_CC_MDSS_VSYNC_CLK_SRC 74 -#define DISP_CC_PLL0 75 -#define DISP_CC_PLL1 76 -#define DISP_CC_SLEEP_CLK 77 -#define DISP_CC_SLEEP_CLK_SRC 78 -#define DISP_CC_XO_CLK 79 -#define DISP_CC_XO_CLK_SRC 80 - -/* DISP_CC resets */ -#define DISP_CC_MDSS_CORE_BCR 0 -#define DISP_CC_MDSS_CORE_INT2_BCR 1 -#define DISP_CC_MDSS_RSCC_BCR 2 - -/* DISP_CC GDSCR */ -#define MDSS_GDSC 0 -#define MDSS_INT2_GDSC 1 - -#endif diff --git a/include/dt-bindings/clock/qcom,sm8650-dispcc.h b/include/dt-bindings/clock/qcom,sm8650-dispcc.h new file mode 120000 index 000000000000..c0a291188f28 --- /dev/null +++ b/include/dt-bindings/clock/qcom,sm8650-dispcc.h @@ -0,0 +1 @@ +qcom,sm8550-dispcc.h \ No newline at end of file
The display clock controller indices for SM8650 and SM8550 are completely equal. Replace the header file for qcom,sm8650-dispcc with the symlink to the qcom,sm8550-dispcc header file. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- include/dt-bindings/clock/qcom,sm8650-dispcc.h | 103 +------------------------ 1 file changed, 1 insertion(+), 102 deletions(-)