From patchwork Mon Jul 22 09:54:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Johan Hovold X-Patchwork-Id: 13738610 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DC9016CD05; Mon, 22 Jul 2024 09:55:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721642120; cv=none; b=ci+liZ+Rmq5dR61gXlV8Ed0KpieqSSMs4ahy+H1dxtiSfgrMBi0mghPXcchumXh+bjW5XpEAjRJw/DvvwOTf/hFCbWgBI/7BU9DGBbDdM+0apqIpcexkNLMW4ACbet363R+iK6OlK8C+9bs4Vt2Smlzo4f2zKXVpReFHPf/WsDE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721642120; c=relaxed/simple; bh=kURi3B16b7OSCk1RbWqrEEd9NL4wjEV60mNcObI8r6U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iLeKwxrQDjls9HFstL8sXf62sLQqcdAA5tItGm0sYFF4g5qzrggXVTqknjy2IywacokzaKcHAuUC0eeZX4J57762f2oKVjp4fwd7/o/3LFMElEGmbzJSVcYzfiFNiByMqZn1Esa5tcLwjdUGaBJYmpb2XbC2FtXiGsE26ZIb7pQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Q/fLyT6I; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Q/fLyT6I" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3A7E0C4AF0A; Mon, 22 Jul 2024 09:55:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1721642120; bh=kURi3B16b7OSCk1RbWqrEEd9NL4wjEV60mNcObI8r6U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q/fLyT6ISZptq+BgwdPddZmMuKhuijqMrxMz2WCXpkTiLeL201POXMFhsCJd8D0Qo /eT+vQfUv6XNBGYHz7yLY1+m0gN5cs0Lv7vFgZBNSFZago7dpalLdRCogO7BBU87oG ost8GNPmXggLjRuK7TbTEpIxxo/4OvziqAeA3hFnQWzhsX4Zr8qaYirmgolTN7IekK h3M+Ts/ZUCIUjEfWFOvE+9yEL4TbMCHuGDw0tWoHt1jZ7K2HHEBES7sEBS7iZKRkMi klz/xQVa64cUN1rjQbX4SuveqKkst9lR1084hCt8//7I6RwAjyzwNrlg6e1pebWxc5 nCK7iYvnzl5/w== Received: from johan by xi.lan with local (Exim 4.97.1) (envelope-from ) id 1sVplH-0000000079Q-1VSG; Mon, 22 Jul 2024 11:55:19 +0200 From: Johan Hovold To: Bjorn Andersson , Konrad Dybcio Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Abel Vesa , Rajendra Nayak , Xilin Wu , Srinivas Kandagatla , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , stable@vger.kernel.org Subject: [PATCH 04/12] arm64: dts: qcom: x1e80100-qcp: fix missing PCIe4 gpios Date: Mon, 22 Jul 2024 11:54:51 +0200 Message-ID: <20240722095459.27437-5-johan+linaro@kernel.org> X-Mailer: git-send-email 2.44.2 In-Reply-To: <20240722095459.27437-1-johan+linaro@kernel.org> References: <20240722095459.27437-1-johan+linaro@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add the missing PCIe4 perst, wake and clkreq GPIOs and pin config. Fixes: f9a9c11471da ("arm64: dts: qcom: x1e80100-qcp: Enable more support") Cc: stable@vger.kernel.org # 6.9 Signed-off-by: Johan Hovold Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 29 +++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts index 998e5ea2f52e..786285af9f33 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts +++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts @@ -572,6 +572,12 @@ &mdss_dp3_phy { }; &pcie4 { + perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie4_default>; + pinctrl-names = "default"; + status = "okay"; }; @@ -665,6 +671,29 @@ nvme_reg_en: nvme-reg-en-state { bias-disable; }; + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins = "gpio147"; + function = "pcie4_clk"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio146"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio148"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + pcie6a_default: pcie6a-default-state { clkreq-n-pins { pins = "gpio153";