[v2,10/10] clk: qcom: camcc-sm8450: Add SM8475 support

Message ID	20240818204348.197788-11-danila@jiaxyga.com (mailing list archive)
State	Accepted
Commit	b815ccf5bfcf95dc2c0a9a421278e0060df35a63
Headers	show Received: from smtp31.i.mail.ru (smtp31.i.mail.ru [95.163.41.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 530CC1586F2; Sun, 18 Aug 2024 20:44:15 +0000 (UTC) From: Danila Tikhonov <danila@jiaxyga.com> To: andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, vladimir.zapolskiy@linaro.org, quic_jkona@quicinc.com, dmitry.baryshkov@linaro.org, konradybcio@kernel.org, quic_tdas@quicinc.com Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux@mainlining.org, Danila Tikhonov <danila@jiaxyga.com> Subject: [PATCH v2 10/10] clk: qcom: camcc-sm8450: Add SM8475 support Date: Sun, 18 Aug 2024 23:43:48 +0300 Message-ID: <20240818204348.197788-11-danila@jiaxyga.com> In-Reply-To: <20240818204348.197788-1-danila@jiaxyga.com> References: <20240818204348.197788-1-danila@jiaxyga.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add SM8475 clock controller drivers \| expand [v2,00/10] Add SM8475 clock controller drivers [v2,01/10] dt-bindings: clock: qcom,gcc-sm8450: Add SM8475 GCC bindings [v2,02/10] clk: qcom: gcc-sm8450: Add SM8475 support [v2,03/10] dt-bindings: clock: qcom,sm8450-dispcc: Add SM8475 DISPCC bindings [v2,04/10] clk: qcom: dispcc-sm8450: Add SM8475 support [v2,05/10] dt-bindings: clock: qcom,sm8450-gpucc: Add SM8475 GPUCC bindings [v2,06/10] clk: qcom: gpucc-sm8450: Add SM8475 support [v2,07/10] dt-bindings: clock: qcom,sm8450-videocc: Add SM8475 VIDEOCC bindings [v2,08/10] clk: qcom: videocc-sm8450: Add SM8475 support [v2,09/10] dt-bindings: clock: qcom,sm8450-camcc: Add SM8475 CAMCC bindings [v2,10/10] clk: qcom: camcc-sm8450: Add SM8475 support

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 8d878bc5f9b8..30eb8236c9d8 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -857,7 +857,7 @@ config SM_CAMCC_8450 depends on ARM64 || COMPILE_TEST select SM_GCC_8450 help - Support for the camera clock controller on SM8450 devices. + Support for the camera clock controller on SM8450 or SM8475 devices. Say Y if you want to support camera devices and camera functionality. config SM_CAMCC_8550 diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c index 26b78eed15ef..08982737e490 100644 --- a/drivers/clk/qcom/camcc-sm8450.c +++ b/drivers/clk/qcom/camcc-sm8450.c @@ -54,6 +54,10 @@ static const struct pll_vco rivian_evo_vco[] = { { 864000000, 1056000000, 0 }, }; +static const struct pll_vco rivian_ole_vco[] = { + { 864000000, 1075000000, 0 }, +}; + static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO }; static const struct alpha_pll_config cam_cc_pll0_config = { @@ -66,6 +70,20 @@ static const struct alpha_pll_config cam_cc_pll0_config = { .user_ctl_hi_val = 0x00000805, }; +static const struct alpha_pll_config sm8475_cam_cc_pll0_config = { + .l = 0x3e, + .alpha = 0x8000, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00008400, + .user_ctl_hi_val = 0x00000005, +}; + static struct clk_alpha_pll cam_cc_pll0 = { .offset = 0x0, .vco_table = lucid_evo_vco, @@ -86,6 +104,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = { { } }; +static struct clk_init_data sm8475_cam_cc_pll0_out_even_init = { + .name = "cam_cc_pll0_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = { .offset = 0x0, .post_div_shift = 10, @@ -109,6 +137,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = { { } }; +static struct clk_init_data sm8475_cam_cc_pll0_out_odd_init = { + .name = "cam_cc_pll0_out_odd", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { .offset = 0x0, .post_div_shift = 14, @@ -137,6 +175,20 @@ static const struct alpha_pll_config cam_cc_pll1_config = { .user_ctl_hi_val = 0x00000805, }; +static const struct alpha_pll_config sm8475_cam_cc_pll1_config = { + .l = 0x25, + .alpha = 0xeaaa, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + static struct clk_alpha_pll cam_cc_pll1 = { .offset = 0x1000, .vco_table = lucid_evo_vco, @@ -157,6 +209,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = { { } }; +static struct clk_init_data sm8475_cam_cc_pll1_out_even_init = { + .name = "cam_cc_pll1_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll1.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { .offset = 0x1000, .post_div_shift = 10, @@ -183,6 +245,16 @@ static const struct alpha_pll_config cam_cc_pll2_config = { .config_ctl_hi1_val = 0x00000217, }; +static const struct alpha_pll_config sm8475_cam_cc_pll2_config = { + .l = 0x32, + .alpha = 0x0, + .config_ctl_val = 0x10000030, + .config_ctl_hi_val = 0x80890263, + .config_ctl_hi1_val = 0x00000217, + .user_ctl_val = 0x00000001, + .user_ctl_hi_val = 0x00000000, +}; + static struct clk_alpha_pll cam_cc_pll2 = { .offset = 0x2000, .vco_table = rivian_evo_vco, @@ -208,6 +280,20 @@ static const struct alpha_pll_config cam_cc_pll3_config = { .user_ctl_hi_val = 0x00000805, }; +static const struct alpha_pll_config sm8475_cam_cc_pll3_config = { + .l = 0x2d, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + static struct clk_alpha_pll cam_cc_pll3 = { .offset = 0x3000, .vco_table = lucid_evo_vco, @@ -228,6 +314,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = { { } }; +static struct clk_init_data sm8475_cam_cc_pll3_out_even_init = { + .name = "cam_cc_pll3_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll3.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { .offset = 0x3000, .post_div_shift = 10, @@ -256,6 +352,20 @@ static const struct alpha_pll_config cam_cc_pll4_config = { .user_ctl_hi_val = 0x00000805, }; +static const struct alpha_pll_config sm8475_cam_cc_pll4_config = { + .l = 0x2d, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + static struct clk_alpha_pll cam_cc_pll4 = { .offset = 0x4000, .vco_table = lucid_evo_vco, @@ -276,6 +386,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = { { } }; +static struct clk_init_data sm8475_cam_cc_pll4_out_even_init = { + .name = "cam_cc_pll4_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll4.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = { .offset = 0x4000, .post_div_shift = 10, @@ -304,6 +424,20 @@ static const struct alpha_pll_config cam_cc_pll5_config = { .user_ctl_hi_val = 0x00000805, }; +static const struct alpha_pll_config sm8475_cam_cc_pll5_config = { + .l = 0x2d, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + static struct clk_alpha_pll cam_cc_pll5 = { .offset = 0x5000, .vco_table = lucid_evo_vco, @@ -324,6 +458,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = { { } }; +static struct clk_init_data sm8475_cam_cc_pll5_out_even_init = { + .name = "cam_cc_pll5_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll5.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = { .offset = 0x5000, .post_div_shift = 10, @@ -352,6 +496,20 @@ static const struct alpha_pll_config cam_cc_pll6_config = { .user_ctl_hi_val = 0x00000805, }; +static const struct alpha_pll_config sm8475_cam_cc_pll6_config = { + .l = 0x2d, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + static struct clk_alpha_pll cam_cc_pll6 = { .offset = 0x6000, .vco_table = lucid_evo_vco, @@ -372,6 +530,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = { { } }; +static struct clk_init_data sm8475_cam_cc_pll6_out_even_init = { + .name = "cam_cc_pll6_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll6.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = { .offset = 0x6000, .post_div_shift = 10, @@ -400,6 +568,20 @@ static const struct alpha_pll_config cam_cc_pll7_config = { .user_ctl_hi_val = 0x00000805, }; +static const struct alpha_pll_config sm8475_cam_cc_pll7_config = { + .l = 0x2d, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + static struct clk_alpha_pll cam_cc_pll7 = { .offset = 0x7000, .vco_table = lucid_evo_vco, @@ -420,6 +602,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = { { } }; +static struct clk_init_data sm8475_cam_cc_pll7_out_even_init = { + .name = "cam_cc_pll7_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll7.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = { .offset = 0x7000, .post_div_shift = 10, @@ -448,6 +640,20 @@ static const struct alpha_pll_config cam_cc_pll8_config = { .user_ctl_hi_val = 0x00000805, }; +static const struct alpha_pll_config sm8475_cam_cc_pll8_config = { + .l = 0x32, + .alpha = 0x0, + .config_ctl_val = 0x20485699, + .config_ctl_hi_val = 0x00182261, + .config_ctl_hi1_val = 0x82aa299c, + .test_ctl_val = 0x00000000, + .test_ctl_hi_val = 0x00000003, + .test_ctl_hi1_val = 0x00009000, + .test_ctl_hi2_val = 0x00000034, + .user_ctl_val = 0x00000400, + .user_ctl_hi_val = 0x00000005, +}; + static struct clk_alpha_pll cam_cc_pll8 = { .offset = 0x8000, .vco_table = lucid_evo_vco, @@ -468,6 +674,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = { { } }; +static struct clk_init_data sm8475_cam_cc_pll8_out_even_init = { + .name = "cam_cc_pll8_out_even", + .parent_hws = (const struct clk_hw*[]) { + &cam_cc_pll8.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_alpha_pll_postdiv_lucid_ole_ops, +}; + static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = { .offset = 0x8000, .post_div_shift = 10, @@ -2817,6 +3033,7 @@ static const struct qcom_cc_desc cam_cc_sm8450_desc = { static const struct of_device_id cam_cc_sm8450_match_table[] = { { .compatible = "qcom,sm8450-camcc" }, + { .compatible = "qcom,sm8475-camcc" }, { } }; MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table); @@ -2829,15 +3046,72 @@ static int cam_cc_sm8450_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); - clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); - clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); - clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); - clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); - clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); - clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); - clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); - clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-camcc")) { + /* Update CAMCC PLL0 */ + cam_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll0_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll0_out_even.clkr.hw.init = &sm8475_cam_cc_pll0_out_even_init; + cam_cc_pll0_out_odd.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll0_out_odd.clkr.hw.init = &sm8475_cam_cc_pll0_out_odd_init; + + /* Update CAMCC PLL1 */ + cam_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll1_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll1_out_even.clkr.hw.init = &sm8475_cam_cc_pll1_out_even_init; + + /* Update CAMCC PLL2 */ + cam_cc_pll2.vco_table = rivian_ole_vco; + + /* Update CAMCC PLL3 */ + cam_cc_pll3.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll3_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll3_out_even.clkr.hw.init = &sm8475_cam_cc_pll3_out_even_init; + + /* Update CAMCC PLL4 */ + cam_cc_pll4.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll4_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll4_out_even.clkr.hw.init = &sm8475_cam_cc_pll4_out_even_init; + + /* Update CAMCC PLL5 */ + cam_cc_pll5.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll5_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll5_out_even.clkr.hw.init = &sm8475_cam_cc_pll5_out_even_init; + + /* Update CAMCC PLL6 */ + cam_cc_pll6.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll6_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll6_out_even.clkr.hw.init = &sm8475_cam_cc_pll6_out_even_init; + + /* Update CAMCC PLL7 */ + cam_cc_pll7.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll7_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll7_out_even.clkr.hw.init = &sm8475_cam_cc_pll7_out_even_init; + + /* Update CAMCC PLL8 */ + cam_cc_pll8.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll8_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; + cam_cc_pll8_out_even.clkr.hw.init = &sm8475_cam_cc_pll8_out_even_init; + + clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &sm8475_cam_cc_pll0_config); + clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &sm8475_cam_cc_pll1_config); + clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &sm8475_cam_cc_pll2_config); + clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &sm8475_cam_cc_pll3_config); + clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &sm8475_cam_cc_pll4_config); + clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &sm8475_cam_cc_pll5_config); + clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &sm8475_cam_cc_pll6_config); + clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &sm8475_cam_cc_pll7_config); + clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &sm8475_cam_cc_pll8_config); + } else { + clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); + clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); + clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); + clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); + clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); + clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); + clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); + clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); + clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); + } return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8450_desc, regmap); } @@ -2852,5 +3126,5 @@ static struct platform_driver cam_cc_sm8450_driver = { module_platform_driver(cam_cc_sm8450_driver); -MODULE_DESCRIPTION("QCOM CAMCC SM8450 Driver"); +MODULE_DESCRIPTION("QCOM CAMCC SM8450 / SM8475 Driver"); MODULE_LICENSE("GPL");

[v2,10/10] clk: qcom: camcc-sm8450: Add SM8475 support

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