diff mbox series

[RFC,06/11] arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on apps_smmu

Message ID 20240919-topic-apps_smmu_coherent-v1-6-5b3a8662403d@quicinc.com (mailing list archive)
State Accepted
Commit 6b31a9744b8726c69bb0af290f8475a368a4b805
Headers show
Series Affirm SMMU coherent pagetable walker capability on RPMh SoCs | expand

Commit Message

Konrad Dybcio Sept. 18, 2024, 10:57 p.m. UTC 
From: Konrad Dybcio <quic_kdybcio@quicinc.com>

On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.

Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 54077549b9da7f0ece69a01d370692d9d716bbb5..49440d1b2cf6caf6da9d97c635cbd751f0700326 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -5159,6 +5159,7 @@  apps_smmu: iommu@15000000 {
 				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
 		};
 
 		anoc_1_tbu: tbu@150c5000 {