Message ID | 20240924100602.3813725-10-vladimir.zapolskiy@linaro.org (mailing list archive) |
---|---|
State | Accepted, archived |
Commit | 7bce7fa2777a5dd73db203df7f063fad1e315f85 |
Headers | show |
Series | arm64: dts: qcom: enable dispcc controllers by default | expand |
On 24/09/2024 12:06, Vladimir Zapolskiy wrote: > After a change enabling display clock controller for all Qualcomm SM8650 > powered board by default there is no more need to set a status property > of dispcc on SM8650-QRD board. > > Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ---- > 1 file changed, 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts > index 8ca0d28eba9b..c5e8c3c2df91 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts > +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts > @@ -741,10 +741,6 @@ vreg_l7n_3p3: ldo7 { > }; > }; > > -&dispcc { > - status = "okay"; > -}; > - > &gpi_dma1 { > status = "okay"; > }; Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index 8ca0d28eba9b..c5e8c3c2df91 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -741,10 +741,6 @@ vreg_l7n_3p3: ldo7 { }; }; -&dispcc { - status = "okay"; -}; - &gpi_dma1 { status = "okay"; };
After a change enabling display clock controller for all Qualcomm SM8650 powered board by default there is no more need to set a status property of dispcc on SM8650-QRD board. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 4 ---- 1 file changed, 4 deletions(-)