| Message ID | 20240925-fix-postdiv-mask-v1-1-f70ba55f415e@mainlining.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set | expand |
On Wed, Sep 25, 2024 at 06:09:39PM GMT, Barnabás Czémán wrote: > Many qcom clock drivers do not have .width set. In that case value of > (p)->width - 1 will be negative which breaks clock tree. Fix this > by checking if width is zero, and pass 0 to GENMASK if that's the case. > > Fixes: 2c4553e6c485 ("clk: qcom: clk-alpha-pll: Fix the pll post div mask") > Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> > --- > drivers/clk/qcom/clk-alpha-pll.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > index f9105443d7dbb104e3cb091e59f43df25999f8b3..1f914bc0af5449ed1fb545d850607138a06fab1a 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.c > +++ b/drivers/clk/qcom/clk-alpha-pll.c > @@ -40,7 +40,7 @@ > > #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) > # define PLL_POST_DIV_SHIFT 8 > -# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) > +# define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 0, 0) I think the actual problem is in the different commit. Commit 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider") made width required, but didn't document it and we did not follow that for a significant amount of PLLs. I think a proper fix should be to return 0xf mask if p->width is 0. In other words, p->width ? p->width-1 : 3 > # define PLL_ALPHA_MSB BIT(15) > # define PLL_ALPHA_EN BIT(24) > # define PLL_ALPHA_MODE BIT(25) > > --- > base-commit: 62f92d634458a1e308bb699986b9147a6d670457 > change-id: 20240925-fix-postdiv-mask-ba47ecd23ea3 > > Best regards, > -- > Barnabás Czémán <barnabas.czeman@mainlining.org> >
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index f9105443d7dbb104e3cb091e59f43df25999f8b3..1f914bc0af5449ed1fb545d850607138a06fab1a 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -40,7 +40,7 @@ #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) # define PLL_POST_DIV_SHIFT 8 -# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) +# define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 0, 0) # define PLL_ALPHA_MSB BIT(15) # define PLL_ALPHA_EN BIT(24) # define PLL_ALPHA_MODE BIT(25)
Many qcom clock drivers do not have .width set. In that case value of (p)->width - 1 will be negative which breaks clock tree. Fix this by checking if width is zero, and pass 0 to GENMASK if that's the case. Fixes: 2c4553e6c485 ("clk: qcom: clk-alpha-pll: Fix the pll post div mask") Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> --- drivers/clk/qcom/clk-alpha-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- base-commit: 62f92d634458a1e308bb699986b9147a6d670457 change-id: 20240925-fix-postdiv-mask-ba47ecd23ea3 Best regards,