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Thu, 03 Oct 2024 01:14:35 -0700 (PDT) Received: from [127.0.1.1] ([178.197.211.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37d082d230dsm702027f8f.94.2024.10.03.01.14.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Oct 2024 01:14:35 -0700 (PDT) From: Krzysztof Kozlowski Date: Thu, 03 Oct 2024 10:14:20 +0200 Subject: [PATCH 3/5] dt-bindings: display/msm: merge SM8350 DPU into SC7280 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241003-dt-binding-display-msm-merge-v1-3-91ab08fc76a2@linaro.org> References: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> In-Reply-To: <20241003-dt-binding-display-msm-merge-v1-0-91ab08fc76a2@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Neil Armstrong , Krishna Manikandan Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Split of the bindings was artificial and not helping - we end up with multiple binding files for very similar devices thus increasing the chances of using different order of reg and clocks entries. Unify DPU bindings of SC7280 and SM8350, because they are the same. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) --- .../bindings/display/msm/qcom,sc7280-dpu.yaml | 1 + .../bindings/display/msm/qcom,sm8350-dpu.yaml | 120 --------------------- 2 files changed, 1 insertion(+), 120 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index fab7a3b9a20e..3d69a573b450 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -17,6 +17,7 @@ properties: enum: - qcom,sc7280-dpu - qcom,sc8280xp-dpu + - qcom,sm8350-dpu reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml deleted file mode 100644 index 96ef2d9c3512..000000000000 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml +++ /dev/null @@ -1,120 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/msm/qcom,sm8350-dpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SM8350 Display DPU - -maintainers: - - Robert Foss - -$ref: /schemas/display/msm/dpu-common.yaml# - -properties: - compatible: - const: qcom,sm8350-dpu - - reg: - items: - - description: Address offset and size for mdp register set - - description: Address offset and size for vbif register set - - reg-names: - items: - - const: mdp - - const: vbif - - clocks: - items: - - description: Display hf axi clock - - description: Display sf axi clock - - description: Display ahb clock - - description: Display lut clock - - description: Display core clock - - description: Display vsync clock - - clock-names: - items: - - const: bus - - const: nrt_bus - - const: iface - - const: lut - - const: core - - const: vsync - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - #include - #include - - display-controller@ae01000 { - compatible = "qcom,sm8350-dpu"; - reg = <0x0ae01000 0x8f000>, - <0x0aeb0000 0x2008>; - reg-names = "mdp", "vbif"; - - clocks = <&gcc GCC_DISP_HF_AXI_CLK>, - <&gcc GCC_DISP_SF_AXI_CLK>, - <&dispcc DISP_CC_MDSS_AHB_CLK>, - <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, - <&dispcc DISP_CC_MDSS_MDP_CLK>, - <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - clock-names = "bus", - "nrt_bus", - "iface", - "lut", - "core", - "vsync"; - - assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; - assigned-clock-rates = <19200000>; - - operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd RPMHPD_MMCX>; - - interrupt-parent = <&mdss>; - interrupts = <0>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dpu_intf1_out: endpoint { - remote-endpoint = <&dsi0_in>; - }; - }; - }; - - mdp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-345000000 { - opp-hz = /bits/ 64 <345000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - - opp-460000000 { - opp-hz = /bits/ 64 <460000000>; - required-opps = <&rpmhpd_opp_nom>; - }; - }; - }; -...