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Fri, 4 Oct 2024 21:24:41 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 14:24:37 -0700 From: Mukesh Ojha To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Konrad Dybcio" , Bartosz Golaszewski , Manivannan Sadhasivam CC: , , , , Mukesh Ojha Subject: [PATCH 6/6] remoteproc: qcom: Enable map/unmap and SHM bridge support Date: Sat, 5 Oct 2024 02:53:59 +0530 Message-ID: <20241004212359.2263502-7-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241004212359.2263502-1-quic_mojha@quicinc.com> References: <20241004212359.2263502-1-quic_mojha@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: O33KIk_m2Wxv9CUVPkpsby8As9vkmR_E X-Proofpoint-ORIG-GUID: O33KIk_m2Wxv9CUVPkpsby8As9vkmR_E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 priorityscore=1501 malwarescore=0 clxscore=1015 phishscore=0 bulkscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040148 For Qualcomm SoCs runnning with Qualcomm EL2 hypervisor(QHEE), IOMMU translation for remote processors is managed by QHEE and if the same SoC run under KVM, remoteproc carveout and devmem region should be IOMMU mapped from Linux PAS driver before remoteproc is brought up and unmapped once it is tear down and apart from this, SHM bridge also need to set up to enable memory protection on both remoteproc meta data memory as well as for the carveout region. Enable the support required to run Qualcomm remoteprocs on non-QHEE hypervisors. Signed-off-by: Mukesh Ojha --- drivers/remoteproc/qcom_q6v5_pas.c | 41 +++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index ac339145e072..13bd13f1b989 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -122,6 +122,7 @@ struct qcom_adsp { struct qcom_devmem_table *devmem; struct qcom_tzmem_area *tzmem; + unsigned long sid; }; static void adsp_segment_dump(struct rproc *rproc, struct rproc_dump_segment *segment, @@ -310,9 +311,21 @@ static int adsp_start(struct rproc *rproc) if (ret) return ret; + ret = qcom_map_unmap_carveout(rproc, adsp->mem_phys, adsp->mem_size, true, true, adsp->sid); + if (ret) { + dev_err(adsp->dev, "iommu mapping failed, ret: %d\n", ret); + goto disable_irqs; + } + + ret = qcom_map_devmem(rproc, adsp->devmem, true, adsp->sid); + if (ret) { + dev_err(adsp->dev, "devmem iommu mapping failed, ret: %d\n", ret); + goto unmap_carveout; + } + ret = adsp_pds_enable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); if (ret < 0) - goto disable_irqs; + goto unmap_devmem; ret = clk_prepare_enable(adsp->xo); if (ret) @@ -400,6 +413,10 @@ static int adsp_start(struct rproc *rproc) clk_disable_unprepare(adsp->xo); disable_proxy_pds: adsp_pds_disable(adsp, adsp->proxy_pds, adsp->proxy_pd_count); +unmap_devmem: + qcom_unmap_devmem(rproc, adsp->devmem, adsp->sid); +unmap_carveout: + qcom_map_unmap_carveout(rproc, adsp->mem_phys, adsp->mem_size, false, true, adsp->sid); disable_irqs: qcom_q6v5_unprepare(&adsp->q6v5); @@ -445,6 +462,9 @@ static int adsp_stop(struct rproc *rproc) dev_err(adsp->dev, "failed to shutdown dtb: %d\n", ret); } + qcom_unmap_devmem(rproc, adsp->devmem, adsp->sid); + qcom_map_unmap_carveout(rproc, adsp->mem_phys, adsp->mem_size, false, true, adsp->sid); + handover = qcom_q6v5_unprepare(&adsp->q6v5); if (handover) qcom_pas_handover(&adsp->q6v5); @@ -844,6 +864,25 @@ static int adsp_probe(struct platform_device *pdev) } platform_set_drvdata(pdev, adsp); + if (of_property_present(pdev->dev.of_node, "iommus")) { + struct of_phandle_args args; + + ret = of_parse_phandle_with_args(pdev->dev.of_node, "iommus", "#iommu-cells", 0, &args); + if (ret < 0) + return ret; + + rproc->has_iommu = true; + adsp->sid = args.args[0]; + of_node_put(args.np); + ret = adsp_devmem_init(adsp); + if (ret) + return ret; + + adsp->pas_metadata.shm_bridge_needed = true; + } else { + rproc->has_iommu = false; + } + ret = device_init_wakeup(adsp->dev, true); if (ret) goto free_rproc;