Message ID | 20241007051255.4378-1-manivannan.sadhasivam@linaro.org (mailing list archive) |
---|---|
State | Not Applicable |
Headers | show |
Series | [v2] PCI: qcom: Enable MSI interrupts together with Link up if 'Global IRQ' is supported | expand |
Hello, > Currently, if 'Global IRQ' is supported by the platform, only the Link up > interrupt is enabled in the PARF_INT_ALL_MASK register. This masks MSIs > on some platforms. The MSI bits in PARF_INT_ALL_MASK register are enabled > by default in the hardware, but commit 4581403f6792 ("PCI: qcom: Enumerate > endpoints based on Link up event in 'global_irq' interrupt") disabled them > and enabled only the Link up interrupt. While MSI continued to work on the > SM8450 platform that was used to test the offending commit, on other > platforms like SM8250, X1E80100, MSIs are getting masked. And they require > enabling the MSI interrupt bits in the register to unmask (enable) the > MSIs. > > Even though the MSI interrupt enable bits in PARF_INT_ALL_MASK are > described as 'diagnostic' interrupts in the internal documentation, > disabling them masks MSI on these platforms. Due to this, MSIs were not > reported to be received these platforms while supporting 'Global IRQ'. > > So enable the MSI interrupts along with the Link up interrupt in the > PARF_INT_ALL_MASK register if 'Global IRQ' is supported. This ensures that > the MSIs continue to work and also the driver is able to catch the Link > up interrupt for enumerating endpoint devices. Applied to controller/qcom, thank you! [01/01] PCI: qcom: Enable MSI interrupts together with Link up if 'Global IRQ' is supported https://git.kernel.org/pci/pci/c/ba4a2e2317b9 Krzysztof
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index ef44a82be058..2b33d03ed054 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -133,6 +133,7 @@ /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ #define PARF_INT_ALL_LINK_UP BIT(13) +#define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23) /* PARF_NO_SNOOP_OVERIDE register fields */ #define WR_NO_SNOOP_OVERIDE_EN BIT(1) @@ -1716,7 +1717,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) goto err_host_deinit; } - writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK); + writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_MSI_DEV_0_7, + pcie->parf + PARF_INT_ALL_MASK); } qcom_pcie_icc_opp_update(pcie);