| Message ID | 20241009-sm8650-v6-11-hmd-pocf-mdss-quad-upstream-21-v2-7-76d4f5d413bf@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | drm/msm/dpu: Support quad pipe with dual-DSI | expand |
On Wed, Oct 09, 2024 at 04:50:20PM GMT, Jun Nie wrote: > There are 2 interfaces and 4 pingpong in quad pipe. Map the 2nd > interface to 3rd PP instead of the 2nd PP. > > Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index bd2509985c4d0..dfe282c607933 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -1100,7 +1100,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, > struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; > struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; > struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; > - int num_lm, num_ctl, num_pp, num_dsc; > + int num_lm, num_ctl, num_pp, num_dsc, num_pp_per_intf; > unsigned int dsc_mask = 0; > int i; > > @@ -1171,9 +1171,14 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, > > cstate->num_dscs = num_dsc; > cstate->num_mixers = num_lm; > - Nit: unrelated > dpu_enc->connector = conn_state->connector; > > + /* > + * There may be 4 PP and 2 INTF for quad pipe case, so INTF is not > + * mapped to PP 1:1. Let's calculate the stride with pipe/INTF > + */ > + num_pp_per_intf = num_lm / dpu_enc->num_phys_encs; > + > for (i = 0; i < dpu_enc->num_phys_encs; i++) { > struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; > struct dpu_hw_ctl *ctl0 = to_dpu_hw_ctl(hw_ctl[0]); > @@ -1195,7 +1200,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, > return; > } > > - phys->hw_pp = dpu_enc->hw_pp[i]; > + phys->hw_pp = dpu_enc->hw_pp[num_pp_per_intf * i]; > > phys->cached_mode = crtc_state->adjusted_mode; > if (phys->ops.atomic_mode_set) > > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index bd2509985c4d0..dfe282c607933 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1100,7 +1100,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; - int num_lm, num_ctl, num_pp, num_dsc; + int num_lm, num_ctl, num_pp, num_dsc, num_pp_per_intf; unsigned int dsc_mask = 0; int i; @@ -1171,9 +1171,14 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, cstate->num_dscs = num_dsc; cstate->num_mixers = num_lm; - dpu_enc->connector = conn_state->connector; + /* + * There may be 4 PP and 2 INTF for quad pipe case, so INTF is not + * mapped to PP 1:1. Let's calculate the stride with pipe/INTF + */ + num_pp_per_intf = num_lm / dpu_enc->num_phys_encs; + for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; struct dpu_hw_ctl *ctl0 = to_dpu_hw_ctl(hw_ctl[0]); @@ -1195,7 +1200,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, return; } - phys->hw_pp = dpu_enc->hw_pp[i]; + phys->hw_pp = dpu_enc->hw_pp[num_pp_per_intf * i]; phys->cached_mode = crtc_state->adjusted_mode; if (phys->ops.atomic_mode_set)
There are 2 interfaces and 4 pingpong in quad pipe. Map the 2nd interface to 3rd PP instead of the 2nd PP. Signed-off-by: Jun Nie <jun.nie@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)