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Thu, 17 Oct 2024 09:28:47 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Oct 2024 02:28:43 -0700 From: Jagadeesh Kona Date: Thu, 17 Oct 2024 14:58:30 +0530 Subject: [PATCH 1/3] arm64: dts: qcom: sa8775p: Add support to scale DDR/L3 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-1-074e0fb80b33@quicinc.com> References: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com> In-Reply-To: <20241017-sa8775p-cpufreq-l3-ddr-scaling-v1-0-074e0fb80b33@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Ajit Pandey , "Imran Shaik" , Taniya Das , "Satya Priya Kakitapalli" , Jagadeesh Kona X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5dl_MOTuKDSef_8MzPAr_XIlZ91Zhtbw X-Proofpoint-ORIG-GUID: 5dl_MOTuKDSef_8MzPAr_XIlZ91Zhtbw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=818 phishscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 clxscore=1015 spamscore=0 suspectscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410170063 Add support to scale DDR and L3 based on CPU frequencies on SA8775P platform. Signed-off-by: Jagadeesh Kona --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 06bf2ba556b89b643da901857a9aa7cdc7ba90cc..d8b90bd4b1f05604185f015929a1f296799ad6a4 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -47,6 +48,10 @@ CPU0: cpu@0 { next-level-cache = <&L2_0>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -69,6 +74,10 @@ CPU1: cpu@100 { next-level-cache = <&L2_1>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; L2_1: l2-cache { compatible = "cache"; cache-level = <2>; @@ -86,6 +95,10 @@ CPU2: cpu@200 { next-level-cache = <&L2_2>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; L2_2: l2-cache { compatible = "cache"; cache-level = <2>; @@ -103,6 +116,10 @@ CPU3: cpu@300 { next-level-cache = <&L2_3>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl0 MASTER_EPSS_L3_APPS + &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; L2_3: l2-cache { compatible = "cache"; cache-level = <2>; @@ -120,6 +137,10 @@ CPU4: cpu@10000 { next-level-cache = <&L2_4>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; L2_4: l2-cache { compatible = "cache"; cache-level = <2>; @@ -143,6 +164,10 @@ CPU5: cpu@10100 { next-level-cache = <&L2_5>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; L2_5: l2-cache { compatible = "cache"; cache-level = <2>; @@ -160,6 +185,10 @@ CPU6: cpu@10200 { next-level-cache = <&L2_6>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; L2_6: l2-cache { compatible = "cache"; cache-level = <2>; @@ -177,6 +206,10 @@ CPU7: cpu@10300 { next-level-cache = <&L2_7>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3_cl1 MASTER_EPSS_L3_APPS + &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; L2_7: l2-cache { compatible = "cache"; cache-level = <2>;