diff mbox series

[3/3] arm64: dts: qcom: qcs615: add AOSS_QMP node

Message ID 20241017025313.2028120-4-quic_chunkaid@quicinc.com (mailing list archive)
State Superseded
Headers show
Series Add aoss_qmp nodes for qcs615 | expand

Commit Message

Kyle Deng Oct. 17, 2024, 2:53 a.m. UTC 
Add the Always-On Subsystem Qualcomm Message Potocol(AOSS_QMP) node for
QCS615 SoC. The AOSS_QMP enables the system to send and receive messages
on the SoC and uses the same hardware version as sdm845.

Signed-off-by: Kyle Deng <quic_chunkaid@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index ac4c4c751da1..a36debf36f82 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -512,6 +512,16 @@  pdc: interrupt-controller@b220000 {
 			interrupt-controller;
 		};
 
+		aoss_qmp: power-controller@c300000 {
+			compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp";
+			reg = <0x0 0x0c300000 0x0 0x400>;
+			interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
+			mboxes = <&apss_shared 0>;
+
+			#clock-cells = <0>;
+			#power-domain-cells = <1>;
+		};
+
 		sram@c3f0000 {
 			compatible = "qcom,rpmh-stats";
 			reg = <0x0 0x0c3f0000 0x0 0x400>;
@@ -528,6 +538,13 @@  intc: interrupt-controller@17a00000 {
 			redistributor-stride = <0x0 0x20000>;
 		};
 
+		apss_shared: mailbox@17c00000 {
+			compatible = "qcom,qcs615-apss-shared",
+				     "qcom,sdm845-apss-shared";
+			reg = <0x0 0x17c00000 0x0 0x1000>;
+			#mbox-cells = <1>;
+		};
+
 		watchdog: watchdog@17c10000 {
 			compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt";
 			reg = <0x0 0x17c10000 0x0 0x1000>;