From patchwork Thu Oct 17 12:36:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan Ramabadhran X-Patchwork-Id: 13839951 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DF101DDC16; Thu, 17 Oct 2024 12:37:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729168672; cv=none; b=InORvNHO4E6ZYpx8kHVTOXkpZSItrCrcF6J4K80jafz2R5Vf0juVJxjyJMXwGfR162ApuwaCsINXZS3tabJPdt3wlQ3vnkEc6zcmck3pIUi1hkpASkcWIq0j0I+5zepQpTFLxJdJdvSGLvKz3dpmuf6lViPH7G2JhXUNH+GOiXg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729168672; c=relaxed/simple; bh=5QLUUpY88aad6Q466F4iZc61jep+6DdrwUN4/IXPVqU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fpJMzLEZKD7Xs/Q6zihP+4PpB9xhgViW257fGYj6DD2ZLMEsRWFGirnTwKuJ3ep7m+heiS+47a1AbZjCA9QHtXBWM7qRHqOLtWlAvtl3yboMERXu/JGCFoTTLAozxqX/DXenGtVUObI/CfEV7vG8kS9yi8LygL58CCBxt8f8jAI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=j718lAKI; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="j718lAKI" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 49HALn7u017516; Thu, 17 Oct 2024 12:37:29 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 2WdjS0kVNWhSBcdzUSNKOn8+YLo4hoECFwvLl0ISqRA=; b=j718lAKI3MhtR+pq OW0wdZZ+n6wU/xM4JrWeL5kwmOsx2O97ukYSkLeu1FcsF9940ITfonwvOBmtLOn0 V07u6Qu0WGIgs8Bqq77npCwEZI963fQR/GvHNzjHSA+DE+zpLvVmMe84+GMWUVTd 4a7NbF6eoisCQ+CDoBiqSE2QuKfSObzeA5IP7mBuwQU0ZdYQeckQrOzWJiaD7vK9 AsvpXyEQHXGCWhTSvLstpZpLc9etWJgjCRFEEjR9fOWksV28SUKZdpFYnkz2y3if G1zG3Z4zRAgphZmR8Z7ggnnMNaLPeQhw6kdHEfuuTDn0P0VZfd3bf5cYubvwj/B+ QKP1tA== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42b0rx0by2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 12:37:29 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49HCbS6p013387 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Oct 2024 12:37:28 GMT Received: from hu-srichara-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 17 Oct 2024 05:37:22 -0700 From: Sricharan R To: , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH V4 6/6] arm64: defconfig: Enable IPQ5424 RDP466 base configs Date: Thu, 17 Oct 2024 18:06:26 +0530 Message-ID: <20241017123626.204421-7-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241017123626.204421-1-quic_srichara@quicinc.com> References: <20241017123626.204421-1-quic_srichara@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: myHeGfUqVx4YwIj4jcsZfgux48kduAKJ X-Proofpoint-ORIG-GUID: myHeGfUqVx4YwIj4jcsZfgux48kduAKJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 spamscore=0 suspectscore=0 impostorscore=0 mlxlogscore=708 malwarescore=0 lowpriorityscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410170086 From: Sricharan Ramabadhran Enable GCC, Pinctrl for Qualcomm's IPQ5424 SoC which is required to boot IPQ5424-RDP466 boards to a console shell. Signed-off-by: Sricharan Ramabadhran Reviewed-by: Krzysztof Kozlowski --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 730f303350c3..4769554977cf 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -596,6 +596,7 @@ CONFIG_PINCTRL_IMX93=y CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_IPQ5018=y CONFIG_PINCTRL_IPQ5332=y +CONFIG_PINCTRL_IPQ5424=y CONFIG_PINCTRL_IPQ8074=y CONFIG_PINCTRL_IPQ6018=y CONFIG_PINCTRL_IPQ9574=y @@ -1310,6 +1311,7 @@ CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_APSS_5018=y CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_5332=y +CONFIG_IPQ_GCC_5424=y CONFIG_IPQ_GCC_6018=y CONFIG_IPQ_GCC_8074=y CONFIG_IPQ_GCC_9574=y