| Message ID | 20241021-sar2130p-clocks-v2-7-383e5eb123a2@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: qcom: add support for clock controllers on the SAR2130P platform | expand |
On 10/21/2024 4:00 PM, Dmitry Baryshkov wrote: > Define clocks as supported by the RPMh on the SAR2130P platform. It > seems that on this platform RPMh models only CXO clock. > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/clk/qcom/clk-rpmh.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c > index 4acde937114af3d7fdc15f3d125a72d42d0fde21..8cb15430d0171a8ed6b05e51d1901af63a4564c4 100644 > --- a/drivers/clk/qcom/clk-rpmh.c > +++ b/drivers/clk/qcom/clk-rpmh.c > @@ -389,6 +389,16 @@ DEFINE_CLK_RPMH_BCM(ipa, "IP0"); > DEFINE_CLK_RPMH_BCM(pka, "PKA0"); > DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0"); > > +static struct clk_hw *sar2130p_rpmh_clocks[] = { > + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw, > + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw, > +}; > + Dimtry, could you please add these clocks as well? DEFINE_CLK_RPMH_VRM-- > rf_clk1, rf_clk1_ao, "clka1", 1 DEFINE_CLK_RPMH_VRM --> ln_bb_clk7, ln_bb_clk7_ao, "clka7", 2 DEFINE_CLK_RPMH_VRM --> ln_bb_clk8, ln_bb_clk8_ao, "clka8", 4 DEFINE_CLK_RPMH_VRM --> ln_bb_clk9, ln_bb_clk9_ao, "clka9", 2 > +static const struct clk_rpmh_desc clk_rpmh_sar2130p = { > + .clks = sar2130p_rpmh_clocks, > + .num_clks = ARRAY_SIZE(sar2130p_rpmh_clocks), > +}; > +
On Tue, 22 Oct 2024 at 09:34, Taniya Das <quic_tdas@quicinc.com> wrote: > > > > On 10/21/2024 4:00 PM, Dmitry Baryshkov wrote: > > Define clocks as supported by the RPMh on the SAR2130P platform. It > > seems that on this platform RPMh models only CXO clock. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > > drivers/clk/qcom/clk-rpmh.c | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c > > index 4acde937114af3d7fdc15f3d125a72d42d0fde21..8cb15430d0171a8ed6b05e51d1901af63a4564c4 100644 > > --- a/drivers/clk/qcom/clk-rpmh.c > > +++ b/drivers/clk/qcom/clk-rpmh.c > > @@ -389,6 +389,16 @@ DEFINE_CLK_RPMH_BCM(ipa, "IP0"); > > DEFINE_CLK_RPMH_BCM(pka, "PKA0"); > > DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0"); > > > > +static struct clk_hw *sar2130p_rpmh_clocks[] = { > > + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw, > > + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw, > > +}; > > + > > Dimtry, could you please add these clocks as well? > > DEFINE_CLK_RPMH_VRM-- > rf_clk1, rf_clk1_ao, "clka1", 1 > DEFINE_CLK_RPMH_VRM --> ln_bb_clk7, ln_bb_clk7_ao, "clka7", 2 > DEFINE_CLK_RPMH_VRM --> ln_bb_clk8, ln_bb_clk8_ao, "clka8", 4 > DEFINE_CLK_RPMH_VRM --> ln_bb_clk9, ln_bb_clk9_ao, "clka9", 2 Just to check, I don't see these clocks being defined in msm-5.10 for the corresponding platform. Am I missing something? > > > +static const struct clk_rpmh_desc clk_rpmh_sar2130p = { > > + .clks = sar2130p_rpmh_clocks, > > + .num_clks = ARRAY_SIZE(sar2130p_rpmh_clocks), > > +}; > > +
On Tue, Oct 22, 2024 at 12:03:57PM +0530, Taniya Das wrote: > > > On 10/21/2024 4:00 PM, Dmitry Baryshkov wrote: > > Define clocks as supported by the RPMh on the SAR2130P platform. It > > seems that on this platform RPMh models only CXO clock. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > > drivers/clk/qcom/clk-rpmh.c | 11 +++++++++++ > > 1 file changed, 11 insertions(+) > > > > diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c > > index 4acde937114af3d7fdc15f3d125a72d42d0fde21..8cb15430d0171a8ed6b05e51d1901af63a4564c4 100644 > > --- a/drivers/clk/qcom/clk-rpmh.c > > +++ b/drivers/clk/qcom/clk-rpmh.c > > @@ -389,6 +389,16 @@ DEFINE_CLK_RPMH_BCM(ipa, "IP0"); > > DEFINE_CLK_RPMH_BCM(pka, "PKA0"); > > DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0"); > > +static struct clk_hw *sar2130p_rpmh_clocks[] = { > > + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw, > > + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw, > > +}; > > + > > Dimtry, could you please add these clocks as well? > > DEFINE_CLK_RPMH_VRM-- > rf_clk1, rf_clk1_ao, "clka1", 1 > DEFINE_CLK_RPMH_VRM --> ln_bb_clk7, ln_bb_clk7_ao, "clka7", 2 > DEFINE_CLK_RPMH_VRM --> ln_bb_clk8, ln_bb_clk8_ao, "clka8", 4 > DEFINE_CLK_RPMH_VRM --> ln_bb_clk9, ln_bb_clk9_ao, "clka9", 2 After checking the CMD-DB, I can see "rfclka1", which I can add, but I don't see clka7/clka8/clka9. Are you sure they are present on the platform? I'll add rfclka1 only for now and skip the rest. > > > +static const struct clk_rpmh_desc clk_rpmh_sar2130p = { > > + .clks = sar2130p_rpmh_clocks, > > + .num_clks = ARRAY_SIZE(sar2130p_rpmh_clocks), > > +}; > > + > > > -- > Thanks & Regards, > Taniya Das.
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index 4acde937114af3d7fdc15f3d125a72d42d0fde21..8cb15430d0171a8ed6b05e51d1901af63a4564c4 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -389,6 +389,16 @@ DEFINE_CLK_RPMH_BCM(ipa, "IP0"); DEFINE_CLK_RPMH_BCM(pka, "PKA0"); DEFINE_CLK_RPMH_BCM(qpic_clk, "QP0"); +static struct clk_hw *sar2130p_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div1.hw, + [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div1_ao.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sar2130p = { + .clks = sar2130p_rpmh_clocks, + .num_clks = ARRAY_SIZE(sar2130p_rpmh_clocks), +}; + static struct clk_hw *sdm845_rpmh_clocks[] = { [RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw, [RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw, @@ -880,6 +890,7 @@ static int clk_rpmh_probe(struct platform_device *pdev) static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000}, { .compatible = "qcom,sa8775p-rpmh-clk", .data = &clk_rpmh_sa8775p}, + { .compatible = "qcom,sar2130p-rpmh-clk", .data = &clk_rpmh_sar2130p}, { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180}, { .compatible = "qcom,sc8180x-rpmh-clk", .data = &clk_rpmh_sc8180x}, { .compatible = "qcom,sc8280xp-rpmh-clk", .data = &clk_rpmh_sc8280xp},
Define clocks as supported by the RPMh on the SAR2130P platform. It seems that on this platform RPMh models only CXO clock. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/clk-rpmh.c | 11 +++++++++++ 1 file changed, 11 insertions(+)