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Thu, 24 Oct 2024 08:10:45 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 24 Oct 2024 01:10:39 -0700 From: Tingguo Cheng Date: Thu, 24 Oct 2024 16:09:48 +0800 Subject: [PATCH v2] arm64: dts: qcom: qcs615: Adds SPMI bus, PMIC and peripherals Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241024-adds-spmi-pmic-peripherals-for-qcs615-v2-1-f262ba243b63@quicinc.com> X-B4-Tracking: v=1; b=H4sIAM4AGmcC/62QQWrDMBBFrxK0ropHliU5q9yjBDMejRpBYjuSY 1pC7l45KZQuugh0ocUX6L3/dRWZU+QstpurSLzEHMehBPWyEXTA4Z1l9CULVSldtaqV6H2WeTp FWQ7JqTyfDpzwmGUYkzxTNtBIMMxNDbZF60VhTYlD/Lh73vaPnPh8Kbr5cfljK/Ligkqp1dXFI c4Rj12+TNOY5q5Ium+JUo0JRmNLSm8XvXp6zCxpPJ3ivN14bmtnwPle9Rh6BrQVuUC6DpUh8t5 UtdG9EmujQ8zzmD7vH7HAvdKTmxeQIHtrbQjOQqhpVwZSHOi1FFrLPXYBPMNrtXfKeAie+A+ef oZnmobRog+A9B88hzUZ693a8xdvf7vdvgDL2uldXgIAAA== X-Change-ID: 20240929-adds-spmi-pmic-peripherals-for-qcs615-16ee53179a7d To: , , , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Tingguo Cheng X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; 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The power key and volume do- wn key are controlled by PMIC PON hardware on pmm6155au. Signed-off-by: Tingguo Cheng --- This patch depends on the patch series: - https://lore.kernel.org/all/20241022-add_initial_support_for_qcs615-v4-0-0a551c6dd342@quicinc.com/ --- Changes in v2: - Include "pm8150.dtsi" for QCS615 PMIC instead of creating a new qcs615-pmic.dtsi in the case that pmm6155au is a variant of pm8150. - Fixed comments from community in V1. - Link to v1: https://lore.kernel.org/r/20241014-adds-spmi-pmic-peripherals-for-qcs615-v1-1-8a3c67d894d8@quicinc.com --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 27 +++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/qcs615.dtsi | 23 +++++++++++++++++++++++ 2 files changed, 50 insertions(+) --- base-commit: de938618db2bafbe1a70c8fc43f06ccdd60364b2 change-id: 20240929-adds-spmi-pmic-peripherals-for-qcs615-16ee53179a7d prerequisite-change-id: 20241022-add_initial_support_for_qcs615-2256f64a9c24:v4 prerequisite-patch-id: 09782474af7eecf1013425fd34f9d2f082fb3616 prerequisite-patch-id: 624720e543d7857e46d3ee49b8cea413772deb4c prerequisite-patch-id: 04ca722967256efddc402b7bab94136a5174b0b9 prerequisite-patch-id: ab88a42ec69ad90e8509c9c5b7c6bdd595a7f783 prerequisite-patch-id: 918724fafe43acaa4c4b980bfabe36e9c3212cd1 prerequisite-patch-id: 3bd8edd83297815fcb1b81fcd891d3c14908442f prerequisite-patch-id: fc1cfec4ecd56e669c161c4d2c3797fc0abff0ae Best regards, diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index ee6cab3924a6d71f29934a8debba3a832882abdd..71ea0cb32eebed713b2a80ab692b14fdb4bd0ce4 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -6,6 +6,7 @@ #include #include "qcs615.dtsi" +#include "pm8150.dtsi" / { model = "Qualcomm Technologies, Inc. QCS615 Ride"; compatible = "qcom,qcs615-ride", "qcom,qcs615"; @@ -210,6 +211,32 @@ &rpmhcc { clocks = <&xo_board_clk>; }; +&spmi_bus { + pmm6155au_0: pmic@0 { + + pon: pon@800 { + + /delete-property/ mode-bootloader; + /delete-property/ mode-recovery; + + pon_pwrkey: pwrkey { + status = "okay"; + }; + + pon_resin: resin { + linux,code = ; + status = "okay"; + }; + }; + + pmm6155au_0_gpios: gpio@c000 {}; + }; + + pmm6155au_1: pmic@1 { + status = "disabled"; + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index ac4c4c751da1fbb28865877555ba317677bc6bd2..3fc928913239cfc61c24d1b16c183b96f38e589d 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -517,6 +517,29 @@ sram@c3f0000 { reg = <0x0 0x0c3f0000 0x0 0x400>; }; + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c440000 0x0 0x1100>, + <0x0 0x0c600000 0x0 0x2000000>, + <0x0 0x0e600000 0x0 0x100000>, + <0x0 0x0e700000 0x0 0xa0000>, + <0x0 0x0c40a000 0x0 0x26000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + cell-index = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */