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Mon, 28 Oct 2024 08:04:21 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 28 Oct 2024 01:04:15 -0700 From: Tingguo Cheng Date: Mon, 28 Oct 2024 16:03:25 +0800 Subject: [PATCH v3 2/2] arm64: dts: qcom: qcs615-ride: Enable PMIC peripherals Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241028-adds-spmi-pmic-peripherals-for-qcs615-v3-2-f0778572ee41@quicinc.com> References: <20241028-adds-spmi-pmic-peripherals-for-qcs615-v3-0-f0778572ee41@quicinc.com> In-Reply-To: <20241028-adds-spmi-pmic-peripherals-for-qcs615-v3-0-f0778572ee41@quicinc.com> To: , , , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Tingguo Cheng X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; a=ed25519-sha256; t=1730102647; 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Signed-off-by: Tingguo Cheng --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index ee6cab3924a6d71f29934a8debba3a832882abdd..37358f080827bbe4484c14c5f159e813810c2119 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -6,6 +6,7 @@ #include #include "qcs615.dtsi" +#include "pm8150.dtsi" / { model = "Qualcomm Technologies, Inc. QCS615 Ride"; compatible = "qcom,qcs615-ride", "qcom,qcs615"; @@ -210,6 +211,20 @@ &rpmhcc { clocks = <&xo_board_clk>; }; +&pon { + /delete-property/ mode-bootloader; + /delete-property/ mode-recovery; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + &uart0 { status = "okay"; };